Toshio Shimada

According to our database1, Toshio Shimada authored at least 22 papers between 1983 and 2008.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2008
Power consumption reduction scheme focusing on the Depth of Speculative Execution.
Proceedings of 8th IEEE International Conference on Computer and Information Technology, 2008

2007
Data prefetching and address pre-calculation through instruction pre-execution with two-step physical register deallocation.
Proceedings of the 2007 workshop on MEmory performance, 2007

2003
Pipeline stage unification: a low-energy consumption technique for future mobile processors.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

2002
A preactivating mechanism for a VT-CMOS cache using address prediction.
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

1999
A 2.5-GFLOPS, 6.5 million polygons per second, four-way VLIW geometry processor with SIMD instructions and a software bypass mechanism.
IEEE J. Solid State Circuits, 1999

An On-Chip Multiprocessor Architecture with a Non-Blocking Synchronization Mechanism.
Proceedings of the 25th EUROMICRO '99 Conference, 1999

1993
The Hardware Architecture of the CODA Real-Time Parallel Processor.
Proceedings of the Parallel Computing: Trends and Applications, 1993

Empirical Study of Latency Hiding on a Fine-Grain Parallel Processor.
Proceedings of the 7th international conference on Supercomputing, 1993

1992
Real-Time Parallel Architecture for Sensor Funsion.
J. Parallel Distributed Comput., 1992

A priority forwarding scheme for real-time multistage interconnection networks.
Proceedings of the Real-Time Systems Symposium, 1992

1991
Parallel Multi-Context Architecture with High-Speed Synchronization Mechanism.
Proceedings of the Fifth International Parallel Processing Symposium, Proceedings, Anaheim, California, USA, April 30, 1991

Sequential description and parallel execution language DFCII dataflow supercomputers.
Proceedings of the 5th international conference on Supercomputing, 1991

1990
Dataflow computer development in Japan.
Proceedings of the 4th international conference on Supercomputing, 1990

1989
Data flow language DFC: Design and implementation.
Syst. Comput. Jpn., 1989

1988
Efficient vector processing on dataflow supercomputer SIGMA-1.
Proceedings of the Proceedings Supercomputing '88, Orlando, FL, USA, November 12-17, 1988, 1988

1987
Load scheduling schemes using inter - PE network.
Syst. Comput. Jpn., 1987

The SIGMA-1 dataflow computer.
Proceedings of the 1987 Fall Joint Computer Conference on Exploring technology: today and tomorrow, 1987

1986
Evaluation of a Prototype Data Flow Processor of the SIGMA-1 for Scientific Computations.
Proceedings of the 13th Annual Symposium on Computer Architecture, Tokyo, Japan, June 1986, 1986

Maintenance Architecture and Its LSI Implementation of a Dataflow Computer with a Large Number of Processors.
Proceedings of the International Conference on Parallel Processing, 1986

1984
Evaluation of Associative Memory Using Parallel Chained Hashing.
IEEE Trans. Computers, 1984

An Architecture of a Data Flow Machine and Its Evaluation.
Proceedings of the COMPCON'84, Digest of Papers, Twenty-Eighth IEEE Computer Society International Conference, San Francisco, California, USA, February 27, 1984

1983
A Control Mechanism of a Lisp-Based Data-Driven Machine.
Inf. Process. Lett., 1983


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