Hideo Maejima

According to our database1, Hideo Maejima authored at least 9 papers between 1983 and 2011.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2011
A 45-nm 37.3 GOPS/W Heterogeneous Multi-Core SOC with 16/32 Bit Instruction-Set General-Purpose Core.
IEICE Trans. Electron., 2011

2010

2009
Domain Partitioning Technology for Embedded Multicore Processors.
IEEE Micro, 2009

TCBC: Trap Caching Bounds Checking for C.
Proceedings of the Eighth IEEE International Conference on Dependable, 2009

1991
Fault-tolerant computer system with stepwise negotiating voting.
Syst. Comput. Jpn., 1991

1989
Circuit technologies for BiCMOS VLSI's as computer elements.
Proceedings of the Computer Design: VLSI in Computers and Processors, 1989

Dependable onboard computer systems with a new method-stepwise negotiating voting.
Proceedings of the Nineteenth International Symposium on Fault-Tolerant Computing, 1989

1986
A 16-Bit Microprocessor with Multi-Register Bank Architecture.
Proceedings of the Fall Joint Computer Conference, November 2-6, 1986, Dallas, Texas, USA, 1986

1983
The VLSI Control Structure of a CMOS Microcomputer.
IEEE Micro, 1983


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