Yasutaka Wada

According to our database, Yasutaka Wada authored at least 29 papers between 2005 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Special Issue on COOL Chips.

Ryusuke Egawa, Yasutaka Wada

IEEE Micro, 2024

2023

Foreword.

Ryusuke Egawa, Yasutaka Wada

IEICE Trans. Electron., June, 2023

Data Transfer API and its Performance Model for Rank-Level Approximate Computing on HPC Systems.

Yoshiyuki Morie, Yasutaka Wada, Ryohei Kobayashi, Ryuichi Sakamoto

Int. J. Netw. Comput., 2023

2022

Performance Evaluation of Data Transfer API for Rank Level Approximate Computing on HPC Systems.

Yoshiyuki Morie, Yasutaka Wada, Ryohei Kobayashi, Ryuichi Sakamoto

Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2022

2021

Efficient and Precise Profiling, Modeling and Management on Power and Performance for Power Constrained HPC Systems.

Yuan He, Yasutaka Wada, Wenchao Luo, Ryuichi Sakamoto, Guanqin Pan, Thang Cao, Masaaki Kondo

IEICE Trans. Electron., 2021

Secure Image Inference Using Pairwise Activation Functions.

Jonas T. Agyepong, Mostafa Soliman, Yasutaka Wada, Keiji Kimura, Ahmed El-Mahdy

IEEE Access, 2021

Mitigating Process Variations with Cooperative Tuning for Performance and Power through a Simple DSL.

Yunjiao Ma, Yuan He, Yasutaka Wada, Wenchao Luo, Ryuichi Sakamoto, Masaaki Kondo

Proceedings of the Ninth International Symposium on Computing and Networking, 2021

An FPGA-Based Image Recognition with Remote Update Functions for Autonomous Driving on "ad-refkit".

Hyuga Hashimoto, Ryo Naka, Yasutaka Wada

Proceedings of the International Conference on Field-Programmable Technology, 2021

2019

Towards the Improvement of Training Efficiency and Image Recognition Accuracy for an FPGA Controlled Mini-Car by Offloading Neural Network Training.

Musashi Aoto, Moe Mitsugi, Takumi Momose, Yasutaka Wada

Proceedings of the International Conference on Field-Programmable Technology, 2019

2018

A Power Management Framework with Simple DSL for Automatic Power-Performance Optimization on Power-Constrained HPC Systems.

Yasutaka Wada, Yuan He, Thang Cao, Masaaki Kondo

Proceedings of the Supercomputing Frontiers - 4th Asian Conference, 2018

Development of an FPGA Controlled "Mini-Car" Toward Autonomous Driving.

Musashi Aoto, Yasutaka Wada, Yousuke Numata

Proceedings of the International Conference on Field-Programmable Technology, 2018

2015

A Linear Time and Space Algorithm for Optimal Traffic-Signal Duration at an Intersection.

Sameh Samra, Ahmed El-Mahdy, Yasutaka Wada

IEEE Trans. Intell. Transp. Syst., 2015

Towards FHE in Embedded Systems: A Preliminary Codesign Space Exploration of a HW/SW Very Large Multiplier.

Ghada Y. Abozaid, Arnaud Tisserand, Ahmed El-Mahdy, Yasutaka Wada

IEEE Embed. Syst. Lett., 2015

Analyzing and mitigating the impact of manufacturing variability in power-constrained supercomputing.

Yuichi Inadomi, Tapasya Patki, Koji Inoue, Mutsumi Aoyagi, Barry Rountree, Martin Schulz, David K. Lowenthal, Yasutaka Wada, Keiichiro Fukazawa, Masatsugu Ueda, Masaaki Kondo, Ikuo Miyoshi

Proceedings of the International Conference for High Performance Computing, 2015

Coarse Grain Task Parallelization of Earthquake Simulator GMS Using OSCAR Compiler on Various Cc-NUMA Servers.

Mamoru Shimaoka, Yasutaka Wada, Keiji Kimura, Hironori Kasahara

Proceedings of the Languages and Compilers for Parallel Computing, 2015

2013

A Linear-Time and Space Algorithm for Optimal Traffic Signal Durations at an Intersection.

Sameh Samra, Ahmed El-Mahdy, Yasutaka Wada

CoRR, 2013

A Scalable Multiplier for Arbitrary Large Numbers Supporting Homomorphic Encryption.

Ghada Y. Abozaid, Ahmed El-Mahdy, Yasutaka Wada

Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

2011

A Parallelizing Compiler Cooperative Heterogeneous Multicore Processor Architecture.

Yasutaka Wada, Akihiro Hayashi, Takeshi Masuura, Jun Shirako, Hirofumi Nakano, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara

Trans. High Perform. Embed. Archit. Compil., 2011

A 45-nm 37.3 GOPS/W Heterogeneous Multi-Core SOC with 16/32 Bit Instruction-Set General-Purpose Core.

Osamu Nishii, Yoichi Yuyama, Masayuki Ito, Yoshikazu Kiyoshige, Yusuke Nitta, Makoto Ishikawa, Tetsuya Yamada, Junichi Miyakoshi, Yasutaka Wada, Keiji Kimura, Hironori Kasahara, Hideo Maejima

IEICE Trans. Electron., 2011

Efficient Parallel Implementations of Controlled Optimization of Traffic Phases.

Sameh Samra, Ahmed El-Mahdy, Walid Gomaa, Yasutaka Wada, Amin A. Shoukry

Proceedings of the Algorithms and Architectures for Parallel Processing, 2011

2010

Parallelizing Compiler Framework and API for Power Reduction and Software Productivity of Real-Time Heterogeneous Multicores.

Akihiro Hayashi, Yasutaka Wada, Takeshi Watanabe, Takeshi Sekiguchi, Masayoshi Mase, Jun Shirako, Keiji Kimura, Hironori Kasahara

Proceedings of the Languages and Compilers for Parallel Computing, 2010

A 45nm 37.3GOPS/W heterogeneous multi-core SoC.

Yoichi Yuyama, Masayuki Ito, Yoshikazu Kiyoshige, Yusuke Nitta, Shigezumi Matsui, Osamu Nishii, Atsushi Hasegawa, Makoto Ishikawa, Tetsuya Yamada, Junichi Miyakoshi, Koichi Terada, Tohru Nojiri, Masashi Satoh, Hiroyuki Mizuno, Kunio Uchiyama, Yasutaka Wada, Keiji Kimura, Hironori Kasahara, Hideo Maejima

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2008

Heterogeneous Multi-Core Architecture That Enables 54x AAC-LC Stereo Encoding.

Hiroaki Shikano, Masaki Ito, Masafumi Onouchi, Takashi Todaka, Takanobu Tsunoda, Tomoyuki Kodama, Kunio Uchiyama, Toshihiko Odaka, Tatsuya Kamei, Ei Nagahama, Manabu Kusaoke, Yusuke Nitta, Yasutaka Wada, Keiji Kimura, Hironori Kasahara

IEEE J. Solid State Circuits, 2008

Power-Aware Compiler Controllable Chip Multiprocessor.

Hiroaki Shikano, Jun Shirako, Yasutaka Wada, Keiji Kimura, Hironori Kasahara

IEICE Trans. Electron., 2008

Parallelization with Automatic Parallelizing Compiler Generating Consumer Electronics Multicore API.

Takamichi Miyamoto, Saori Asaka, Hiroki Mikami, Masayoshi Mase, Yasutaka Wada, Hirofumi Nakano, Keiji Kimura, Hironori Kasahara

Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2008

Software-cooperative power-efficient heterogeneous multi-core for media processing.

Hiroaki Shikano, Masaki Ito, Kunio Uchiyama, Toshihiko Odaka, Akihiro Hayashi, Takeshi Masuura, Masayoshi Mase, Jun Shirako, Yasutaka Wada, Keiji Kimura, Hironori Kasahara

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2005

Compiler Control Power Saving Scheme for Multi Core Processors.

Jun Shirako, Naoto Oshiyama, Yasutaka Wada, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara

Proceedings of the Languages and Compilers for Parallel Computing, 2005

Performance Evaluation of Compiler Controlled Power Saving Scheme.

Jun Shirako, Munehiro Yoshida, Naoto Oshiyama, Yasutaka Wada, Hirofumi Nakano, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara

Proceedings of the High-Performance Computing - 6th International Symposium, 2005

Multigrain parallel processing on compiler cooperative chip multiprocessor.

Keiji Kimura, Yasutaka Wada, Hirofumi Nakano, Takeshi Kodaka, Jun Shirako, Kazuhisa Ishizaka, Hironori Kasahara

Proceedings of the 9th Annual Workshop on Interaction between Compilers and Computer Architectures, 2005