Yusuke Nitta

According to our database1, Yusuke Nitta authored at least 8 papers between 1993 and 2011.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2011
A 45-nm 37.3 GOPS/W Heterogeneous Multi-Core SOC with 16/32 Bit Instruction-Set General-Purpose Core.
IEICE Trans. Electron., 2011

2010

2008
Heterogeneous Multi-Core Architecture That Enables 54x AAC-LC Stereo Encoding.
IEEE J. Solid State Circuits, 2008

2007
Embedded SoC Resource Manager to Control Temperature and Data Bandwidth.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2006
Reducing Consuming Clock Power Optimization of a 90 nm Embedded Processor Core.
IEICE Trans. Electron., 2006

2005
Low-Power Design of 90-nm SuperH Processor Core.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

1998
Design Methodology of a 200MHz Superscalar Microprocessor: SH-4.
Proceedings of the 35th Conference on Design Automation, 1998

1993
Generation of a hierarchical representation for graphic patterns based on grouping.
Syst. Comput. Jpn., 1993


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