Hirohito Kikukawa

According to our database, Hirohito Kikukawa authored at least 4 papers between 2001 and 2007.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2007

A PND (PMOS-NMOS-Depletion MOS) Type Single Poly Gate Non-Volatile Memory Cell Design with a Differential Cell Architecture in a Pure CMOS Logic Process for a System LSI.

Yasue Yamamoto, Masanori Shirahama, Toshiaki Kawasaki, Ryuji Nishihara, Shinichi Sumi, Yasuhiro Agata, Hirohito Kikukawa, Hiroyuki Yamauchi

IEICE Trans. Electron., 2007

2005

A 400-MHz random-cycle dual-port interleaved DRAM (D²RAM) with standard CMOS Process.

Masanori Shirahama, Yasuhiro Agata, Toshiaki Kawasaki, Ryuji Nishihara, Wataru Abe, Naoki Kuroda, Hiroyuki Sadakata, Toshitaka Uchikoba, Kazunari Takahashi, Kyoko Egashira, Shinji Honda, Miho Miura, Shin Hashimoto, Hirohito Kikukawa, Hiroyuki Yamauchi

IEEE J. Solid State Circuits, 2005

2002

0.13-μm 32-Mb/64-Mb embedded DRAM core with high efficient redundancy and enhanced testability.

Hirohito Kikukawa, Shigeki Tomishima, Takaharu Tsuji, Toshiaki Kawasaki, Shouji Sakamoto, Masatoshi Ishikawa, Wataru Abe, Hiroaki Tanizaki, Hiroshi Kato, Toshitaka Uchikoba, Toshihiro Inokuchi, Manabu Senoh, Yoshifumi Fukushima, Mitsutaka Niiro, Masanao Maruta, Akinori Shibayama, Tsukasa Ooishi, Kazunari Takahashi, Hideto Hidaka

IEEE J. Solid State Circuits, 2002

2001

A 1.0-V 230-MHz column access embedded DRAM for portable MPEG applications.

Shigeki Tomishima, Takaharu Tsuji, Toshiaki Kawasaki, Masatoshi Ishikawa, Toshihiro Inokuchi, Hiroshi Kato, Hiroaki Tanizaki, Wataru Abe, Akinori Shibayama, Yoshifumi Fukushima, Mitsutaka Niiro, Masanao Maruta, Toshitaka Uchikoba, Manabu Senoh, Shouji Sakamoto, Tsukasa Ooishi, Hirohito Kikukawa, Hideto Hidaka, Kazunari Takahashi

IEEE J. Solid State Circuits, 2001