Hiroyuki Yamauchi
Orcid: 0000-0003-4033-8893
According to our database1,
Hiroyuki Yamauchi
authored at least 58 papers
between 1980 and 2023.
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Bibliography
2023
Image Recognition Accuracy, Number of Parameters and Computational Complexity Using Channel Reduction by Dimensional Compression and Attention Function.
Proceedings of the 6th International Conference on Electronics, 2023
Graph Structure Exploration for Reinforcement Learning State Embedding - Train Tetris Agent with Graph Neural Network.
Proceedings of the 6th International Conference on Electronics, 2023
2022
A Machine Learning Based Fuel Consumption Saving Method with Time and Environment Dependency Aware Management.
Proceedings of the ICECC 2022: The 5th International Conference on Electronics, Communications and Control Engineering, Higashi-ku, Japan, March 25, 2022
2021
Int. J. Pattern Recognit. Artif. Intell., 2021
2019
A Dual-Split 6T SRAM-Based Computing-in-Memory Unit-Macro With Fully Parallel Product-Sum Operation for Binarized DNN Edge Processors.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
A 28-nm 320-Kb TCAM Macro Using Split-Controlled Single-Load 14T Cell and Triple-Margin Voltage Sense Amplifier.
IEEE J. Solid State Circuits, 2019
2018
PeerJ Prepr., 2018
A 28mn 320Kb TCAM Macro with Sub-0.8ns Search Time and 3.5+x Improvement in Delay-Area-Energy Product using Split-Controlled Single-Load 14T Cell.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018
2017
A Compact-Area Low-VDDmin 6T SRAM With Improvement in Cell Stability, Read Speed, and Write Margin Using a Dual-Split-Control-Assist Scheme.
IEEE J. Solid State Circuits, 2017
2016
A mutual rectification-interference avoidance technique with cascade filters for both downward-direction tailed-RDF deconvolution.
Proceedings of the 29th Symposium on Integrated Circuits and Systems Design, 2016
A filter design for blind deconvolution to decouple unknown RDF/RTN factors from complexly coupled SRAM margin variations.
Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016
2015
A filter design to increase accuracy of Lucy-Richardson deconvolution for analyzing RTN mixtures effects on VLSI reliability margin.
Proceedings of the 28th IEEE International System-on-Chip Conference, 2015
A Phase Shifting Multiple Filter Design Methodology for Lucy-Richardson Deconvolution of Log-Mixtures Complex RTN Tail Distribution.
Proceedings of the 28th Symposium on Integrated Circuits and Systems Design, 2015
Feedback gain phase alignment effects on convergence characteristics in Lucy-Richardson deconvolution for inversely predicting complex-shaped RTN distributions.
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015
Ringing error prevention techniques in Lucy-Richardson deconvolution process for SRAM space-time margin variation effect screening designs.
Proceedings of the 16th Latin-American Test Symposium, 2015
17.3 A 28nm 256kb 6T-SRAM with 280mV improvement in VMIN using a dual-split-control assist scheme.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
2014
An RTN Variation Tolerant SRAM Screening Test Design with Gaussian Mixtures Approximations of Long-Tail Distributions.
J. Electron. Test., 2014
Deconvolution algorithm dependencies of estimation errors of RTN effects on subnano-scaled SRAM margin variation.
Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014
Errors in solving inverse problem for reversing RTN effects on VCCmin shift in SRAM reliability screening test designs.
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014
Comparative study on deconvolution function dependencies of RTN/RDF effect estimation errors in analyzing sub-nm-scaled SRAM margins.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014
A technique to solve issue of Richardson-Lucy deconvolution for analyzing RTN effects on SRAM margin variation.
Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014
2013
Low-Voltage Embedded NAND-ROM Macros Using Data-Aware Sensing Reference Scheme for VDDmin, Speed and Power Improvement.
IEEE J. Solid State Circuits, 2013
An Offset-Tolerant Fast-Random-Read Current-Sampling-Based Sense Amplifier for Small-Cell-Current Nonvolatile Memory.
IEEE J. Solid State Circuits, 2013
A Sub-0.3 V Area-Efficient L-Shaped 7T SRAM With Read Bitline Swing Expansion Schemes Based on Boosted Read-Bitline, Asymmetric-V<sub>TH</sub> Read-Port, and Offset Cell VDD Biasing Techniques.
IEEE J. Solid State Circuits, 2013
A RTN variation tolerant guard band design for a deeper nanometer scaled SRAM screening test: Based on EM Gaussians mixtures approximations model of long-tail distributions.
Proceedings of the 14th Latin American Test Workshop, 2013
A discussion on SRAM forward/inverse problem analyses for RTN long-tail distributions.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013
Convolution/deconvolution SRAM analyses for complex gamma mixtures RTN distributions.
Proceedings of 2013 International Conference on IC Design & Technology, 2013
2012
Compact Measurement Schemes for Bit-Line Swing, Sense Amplifier Offset Voltage, and Word-Line Pulse Width to Characterize Sensing Tolerance Margin in a 40 nm Fully Functional Embedded SRAM.
IEEE J. Solid State Circuits, 2012
A 260mV L-shaped 7T SRAM with bit-line (BL) Swing expansion schemes based on boosted BL, asymmetric-VTH read-port, and offset cell VDD biasing techniques.
Proceedings of the Symposium on VLSI Circuits, 2012
Endurance-aware circuit designs of nonvolatile logic and nonvolatile sram using resistive memory (memristor) device.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
2011
A Large Sigma V <sub>TH</sub> /VDD Tolerant Zigzag 8T SRAM With Area-Efficient Decoupled Differential Sensing and Fast Write-Back Scheme.
IEEE J. Solid State Circuits, 2011
An offset-tolerant current-sampling-based sense amplifier for Sub-100nA-cell-current nonvolatile memory.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
2010
IEEE Trans. Very Large Scale Integr. Syst., 2010
A Differential Data-Aware Power-Supplied (D <sup>2</sup> AP) 8T SRAM Cell With Expanded Write/Read Stabilities for Lower VDDmin Applications.
IEEE J. Solid State Circuits, 2010
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
2009
A 0.6 V Dual-Rail Compiler SRAM Design on 45 nm CMOS Technology With Adaptive SRAM Power for Lower VDD_min VLSIs.
IEEE J. Solid State Circuits, 2009
2008
An Over-1-Gb/s Transceiver Core for Integration Into Large System-on-Chips for Consumer Electronics.
IEEE Trans. Very Large Scale Integr. Syst., 2008
A Stable 2-Port SRAM Cell Design Against Simultaneously Read/Write-Disturbed Accesses.
IEEE J. Solid State Circuits, 2008
2007
A 1R/1W SRAM Cell Design to Keep Cell Current and Area Saving against Simultaneous Read/Write Disturbed Accesses.
IEICE Trans. Electron., 2007
A PND (PMOS-NMOS-Depletion MOS) Type Single Poly Gate Non-Volatile Memory Cell Design with a Differential Cell Architecture in a Pure CMOS Logic Process for a System LSI.
IEICE Trans. Electron., 2007
Proceedings of the 2007 IEEE International SOC Conference, 2007
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
A Stable SRAM Mitigating Cell-Margin Asymmetricity with A Disturb-Free Biasing Scheme.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
2006
A sub-0.5-V operating embedded SRAM featuring a multi-bit-error-immune hidden-ECC scheme.
IEEE J. Solid State Circuits, 2006
A Differential Cell Terminal Biasing Scheme Enabling a Stable Write Operation against a Large Random Threshold Voltage (<i>V</i><sub>th</sub>) Variation.
IEICE Trans. Electron., 2006
2005
A 400-MHz random-cycle dual-port interleaved DRAM (D<sup>2</sup>RAM) with standard CMOS Process.
IEEE J. Solid State Circuits, 2005
IEEE J. Solid State Circuits, 2005
0.3-1.5 V Embedded SRAM Core with Write-Replica Circuit Using Asymmetrical Memory Cell and Source-Level-Adjusted Direct-Sense-Amplifier.
IEICE Trans. Electron., 2005
2000
Proceedings of the Foundations of Intelligent Systems, 12th International Symposium, 2000
1999
Incorporating Fuzzy Set Theory and Matrix Logic in Multi-Layer Logic - A Preliminary Consideration.
Proceedings of the New Directions in Rough Sets, 1999
1997
A 0.5 V single power supply operated high-speed boosted and offset-grounded data storage (BOGS) SRAM cell architecture.
IEEE Trans. Very Large Scale Integr. Syst., 1997
1996
A signal-swing suppressing strategy for power and layout area savings using time-multiplexed differential data-transfer scheme.
IEEE J. Solid State Circuits, 1996
A 0.5V/100 MHz over-VCC grounded data storage (OVGS) SRAM cell architecture with boosted bit-line and offset source over-driving schemes.
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996
1995
A circuit technology for a self-refresh 16 Mb DRAM with less than 0.5 μA/MB data-retention current.
IEEE J. Solid State Circuits, November, 1995
An asymptotically zero power charge-recycling bus architecture for battery-operated ultrahigh data rate ULSI's.
IEEE J. Solid State Circuits, April, 1995
1990
1985
Multi-Layer Logic - A Predicate Logic Including Data Structure as Knowledge Representation Language.
New Gener. Comput., 1985
1980
Processing Of Syntax And Semantics Of Natural Language By Predicate Logic Of Predicate Logic.
Proceedings of the 8th International Conference on Computational Linguistics, 1980