Masanao Maruta

According to our database, Masanao Maruta authored at least 5 papers between 2001 and 2005.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2005

A 322 MHz random-cycle embedded DRAM with high-accuracy sensing and tuning.

Masahisa Iida, Naoki Kuroda, Hidefumi Otsuka, Masanobu Hirose, Yuji Yamasaki, Kiyoto Ohta, Kazuhiko Shimakawa, Takashi Nakabayashi, Hiroyuki Yamauchi, Tomohiko Sano, Takayuki Gyohten, Masanao Maruta, Akira Yamazaki, Fukashi Morishita, Katsumi Dosaka, Masahiko Takeuchi, Kazutami Arimoto

IEEE J. Solid State Circuits, 2005

2002

0.13-μm 32-Mb/64-Mb embedded DRAM core with high efficient redundancy and enhanced testability.

Hirohito Kikukawa, Shigeki Tomishima, Takaharu Tsuji, Toshiaki Kawasaki, Shouji Sakamoto, Masatoshi Ishikawa, Wataru Abe, Hiroaki Tanizaki, Hiroshi Kato, Toshitaka Uchikoba, Toshihiro Inokuchi, Manabu Senoh, Yoshifumi Fukushima, Mitsutaka Niiro, Masanao Maruta, Akinori Shibayama, Tsukasa Ooishi, Kazunari Takahashi, Hideto Hidaka

IEEE J. Solid State Circuits, 2002

A Variable Drivability (VD) Output Buffer for the System In a Package (SIP) and High Frequency Wafer Test.

Shigeki Tomishima, Hiroaki Tanizaki, Mitsutaka Niiro, Masanao Maruta, Hideto Hidaka, T. Tada, Kenji Gamo

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

2001

A 1.0-V 230-MHz column access embedded DRAM for portable MPEG applications.

Shigeki Tomishima, Takaharu Tsuji, Toshiaki Kawasaki, Masatoshi Ishikawa, Toshihiro Inokuchi, Hiroshi Kato, Hiroaki Tanizaki, Wataru Abe, Akinori Shibayama, Yoshifumi Fukushima, Mitsutaka Niiro, Masanao Maruta, Toshitaka Uchikoba, Manabu Senoh, Shouji Sakamoto, Tsukasa Ooishi, Hirohito Kikukawa, Hideto Hidaka, Kazunari Takahashi

IEEE J. Solid State Circuits, 2001

A shared built-in self-repair analysis for multiple embedded memories.

Jun Ohtani, Tukasa Ooishi, Tomoya Kawagoe, Mitsutaka Niiro, Masanao Maruta, Hideto Hidaka

Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001