Hirokatsu Shirahama

According to our database, Hirokatsu Shirahama authored at least 12 papers between 2006 and 2014.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2014

High-Throughput Partially Parallel Inter-Chip Link Architecture for Asynchronous Multi-Chip NoCs.

Naoya Onizawa, Akira Mochizuki, Hirokatsu Shirahama, Masashi Imai, Tomohiro Yoneda, Takahiro Hanyu

IEICE Trans. Inf. Syst., 2014

Design of an Energy-Efficient Ternary Current-Mode Intra-Chip Communication Link for an Asynchronous Network-on-Chip.

Akira Mochizuki, Hirokatsu Shirahama, Yuma Watanabe, Takahiro Hanyu

IEICE Trans. Inf. Syst., 2014

Design of a Quaternary Single-Ended Current-Mode Circuit for an Energy-Efficient Inter-chip Asynchronous Communication Link.

Akira Mochizuki, Hirokatsu Shirahama, Takahiro Hanyu

Proceedings of the IEEE 44th International Symposium on Multiple-Valued Logic, 2014

Energy-aware current-mode inter-chip link for a dependable GALS NoC platform.

Hirokatsu Shirahama, Akira Mochizuki, Yuma Watanabe, Takahiro Hanyu

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Highly reliable single-ended current-mode circuit for an inter-chip asynchronous communication link.

Akira Mochizuki, Hirokatsu Shirahama, Naoya Onizawa, Takahiro Hanyu

Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

2010

Energy-Aware Multiple-Valued Current-Mode Sequential Circuits Using a Completion-Detection Scheme.

Hirokatsu Shirahama, Takashi Matsuura, Masanori Natsui, Takahiro Hanyu

IEICE Trans. Inf. Syst., 2010

2009

Timing-Variation-Aware Multiple-Valued Current-Mode Circuit for a Low-Power Pipelined System.

Takashi Matsuura, Hirokatsu Shirahama, Masanori Natsui, Takahiro Hanyu

Proceedings of the ISMVL 2009, 2009

2008

Design of High-Performance Quaternary Adders Based on Output-Generator Sharing.

Hirokatsu Shirahama, Takahiro Hanyu

Proceedings of the 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 2008

2007

Design and Evaluation of a 54 x 54-bit Multiplier Based on Differential-Pair Circuitry.

Akira Mochizuki, Hirokatsu Shirahama, Takahiro Hanyu

IEICE Trans. Electron., 2007

Design of a Processing Element Based on Quaternary Differential Logic for a Multi-Core SIMD Processor.

Hirokatsu Shirahama, Akira Mochizuki, Takahiro Hanyu, Masami Nakajima, Kazutami Arimoto

Proceedings of the 37th International Symposium on Multiple-Valued Logic, 2007

2006

Design of a Low-Power Quaternary Flip-Flop Based on Dynamic Differential Logic.

Akira Mochizuki, Hirokatsu Shirahama, Takahiro Hanyu

IEICE Trans. Electron., 2006

Design of a Microprocessor Datapath Using Four-Valued Differential-Pair Circuits.

Akira Mochizuki, Takeshi Kitamura, Hirokatsu Shirahama, Takahiro Hanyu

Proceedings of the 36th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2006), 2006