Akira Mochizuki

According to our database, Akira Mochizuki authored at least 29 papers between 1992 and 2017.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2017

Sudden Power-Outage Resilient In-Processor Checkpointing for Energy-Harvesting Nonvolatile Processors.

Naoya Onizawa, Akira Mochizuki, Akira Tamakoshi, Takahiro Hanyu

IEEE Trans. Emerg. Top. Comput., 2017

2016

Stochastic behavior-considered VLSI CAD environment for MTJ/MOS-hybrid microprocessor design.

Masanori Natsui, Akira Tamakoshi, Akira Mochizuki, Hiroki Koike, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015

Fabrication of a 3000-6-input-LUTs embedded and block-level power-gated nonvolatile FPGA chip using p-MTJ-based logic-in-memory structure.

Daisuke Suzuki, Masanori Natsui, Akira Mochizuki, Sadahiko Miura, Hiroaki Honjo, Hideo Sato, Shunsuke Fukami, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu

Proceedings of the Symposium on VLSI Circuits, 2015

A sudden power-outage resilient nonvolatile microprocessor for immediate system recovery.

Naoya Onizawa, Akira Mochizuki, Akira Tamakoshi, Takahiro Hanyu

Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015

Design of a computational nonvolatile RAM for a greedy energy-efficient VLSI processor.

Akira Mochizuki, Naoto Yube, Takahiro Hanyu

Proceedings of the IECON 2015, 2015

Spintronics-based nonvolatile logic-in-memory architecture towards an ultra-low-power and highly reliable VLSI computing paradigm.

Takahiro Hanyu, Daisuke Suzuki, Naoya Onizawa, Shoun Matsunaga, Masanori Natsui, Akira Mochizuki

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014

High-Throughput Partially Parallel Inter-Chip Link Architecture for Asynchronous Multi-Chip NoCs.

Naoya Onizawa, Akira Mochizuki, Hirokatsu Shirahama, Masashi Imai, Tomohiro Yoneda, Takahiro Hanyu

IEICE Trans. Inf. Syst., 2014

Design of an Energy-Efficient Ternary Current-Mode Intra-Chip Communication Link for an Asynchronous Network-on-Chip.

Akira Mochizuki, Hirokatsu Shirahama, Yuma Watanabe, Takahiro Hanyu

IEICE Trans. Inf. Syst., 2014

A compact low-power nonvolatile flip-flop using domain-wall-motion-device-based single-ended structure.

Daisuke Suzuki, Noboru Sakimura, Masanori Natsui, Akira Mochizuki, Tadahiko Sugibayashi, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu

IEICE Electron. Express, 2014

Complementary 5T-4MTJ nonvolatile TCAM cell circuit with phase-selective parallel writing scheme.

Shoun Matsunaga, Akira Mochizuki, Noboru Sakimura, Ryusuke Nebashi, Tadahiko Sugibayashi, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu

IEICE Electron. Express, 2014

Design of an energy-efficient 2T-2MTJ nonvolatile TCAM based on a parallel-serial-combined search scheme.

Shoun Matsunaga, Akira Mochizuki, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu

IEICE Electron. Express, 2014

Design of a Quaternary Single-Ended Current-Mode Circuit for an Energy-Efficient Inter-chip Asynchronous Communication Link.

Akira Mochizuki, Hirokatsu Shirahama, Takahiro Hanyu

Proceedings of the IEEE 44th International Symposium on Multiple-Valued Logic, 2014

Energy-aware current-mode inter-chip link for a dependable GALS NoC platform.

Hirokatsu Shirahama, Akira Mochizuki, Yuma Watanabe, Takahiro Hanyu

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Highly reliable single-ended current-mode circuit for an inter-chip asynchronous communication link.

Akira Mochizuki, Hirokatsu Shirahama, Naoya Onizawa, Takahiro Hanyu

Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

2013

Fabrication of a magnetic tunnel junction-based 240-tile nonvolatile field-programmable gate array chip skipping wasted write operations for greedy power-reduced logic applications.

Daisuke Suzuki, Masanori Natsui, Akira Mochizuki, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Hideo Sato, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu

IEICE Electron. Express, 2013

2007

Design and Evaluation of a 54 x 54-bit Multiplier Based on Differential-Pair Circuitry.

Akira Mochizuki, Hirokatsu Shirahama, Takahiro Hanyu

IEICE Trans. Electron., 2007

Design of a Processing Element Based on Quaternary Differential Logic for a Multi-Core SIMD Processor.

Hirokatsu Shirahama, Akira Mochizuki, Takahiro Hanyu, Masami Nakajima, Kazutami Arimoto

Proceedings of the 37th International Symposium on Multiple-Valued Logic, 2007

High-Performance Multiple-Valued Comparator Based on Active-Load Dual-Rail Differential Logic for Crosstalk-Noise Reduction.

Akira Mochizuki, Masatomo Miura, Takahiro Hanyu

Proceedings of the 37th International Symposium on Multiple-Valued Logic, 2007

2006

Design of a Low-Power Quaternary Flip-Flop Based on Dynamic Differential Logic.

Akira Mochizuki, Hirokatsu Shirahama, Takahiro Hanyu

IEICE Trans. Electron., 2006

Design of a Microprocessor Datapath Using Four-Valued Differential-Pair Circuits.

Akira Mochizuki, Takeshi Kitamura, Hirokatsu Shirahama, Takahiro Hanyu

Proceedings of the 36th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2006), 2006

Highly reliable Multiple-Valued Circuit Based on Dual-Rail Differential Logic.

Akira Mochizuki, Takahiro Hanyu

Proceedings of the 36th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2006), 2006

2005

Design of a Low-Power Multiple-Valued Integrated Circuit Based on Dynamic Source-Coupled Logic.

Akira Mochizuki, Takahiro Hanyu, Michitaka Kameyama

J. Multiple Valued Log. Soft Comput., 2005

TMR-Based Logic-in-Memory Circuit for Low-Power VLSI.

Akira Mochizuki, Hiromitsu Kimura, Mitsuru Ibuki, Takahiro Hanyu

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

Multiple-Valued Duplex Asynchronous Data Transfer Scheme for Interleaving in LDPC Decoders.

Naoya Onizawa, Akira Mochizuki, Takahiro Hanyu

Proceedings of the 35th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2005), 2005

2004

Intra-Chip Address-Presetting Data-Transfer Scheme Using Four-Valued Encoding.

Akira Mochizuki, Takashi Takeuchi, Takahiro Hanyu

Proceedings of the 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2004), 2004

2003

Multiple-Valued Dynamic Source-Coupled Logic.

Takahiro Hanyu, Akira Mochizuki, Michitaka Kameyama

Proceedings of the 33rd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2003), 2003

1995

Multiple-Valued Arithmetic Integrated Circuits Based on 1.5V-Supply Dual-Rail Source-Coupled Logic.

Takahiro Hanyu, Akira Mochizuki, Michitaka Kameyama

Proceedings of the 25th IEEE International Symposium on Multiple-Valued Logic, 1995

1994

Multiple-Valued Current-Mode MOS Integrated Circuits Based on Dual-Rail Source-Coupled Logic.

Takahiro Hanyu, Akira Mochizuki, Michitaka Kameyama

Proceedings of the 24th IEEE International Symposium on Multiple-Valued Logic, 1994

1992

Three-Dimensional Tactile Display by Multi-Stage Actuator.

Masami Shinohara, Shinya Saida, Yutaka Shimizu, Akira Mochizuki, Kanehiro Sorimachi

J. Robotics Mechatronics, 1992