Naoya Onizawa
Orcid: 0000-0002-4855-7081
According to our database1,
Naoya Onizawa
authored at least 105 papers
between 2005 and 2023.
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Bibliography
2023
Fast-Converging Simulated Annealing for Ising Models Based on Integral Stochastic Computing.
IEEE Trans. Neural Networks Learn. Syst., December, 2023
IEEE J. Emerg. Sel. Topics Circuits Syst., March, 2023
Local Energy Distribution Based Hyperparameter Determination for Stochastic Simulated Annealing.
CoRR, 2023
Stochastic Quantum Monte Carlo Algorithm for Large-Scale Combinatorial Optimization Problems.
CoRR, 2023
Self-Adaptive Gate Control for Efficient Escape From Local Minimum Energy on Invertible Logic.
IEEE Access, 2023
Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023
Proceedings of the International Conference on Field Programmable Technology, 2023
2022
Implementation of CMOS Invertible Logic on Zynq-SoC Platform: A Case Study of Training BNN.
FLAP, 2022
Fast Solving Complete 2000-Node Optimization Using Stochastic-Computing Simulated Annealing.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022
2021
Multi-Context TCAM-Based Selective Computing: Design Space Exploration for a Low-Power NN.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
Hardware Acceleration of Large-Scale CMOS Invertible Logic Based on Sparse Hamiltonian Matrices.
IEEE Open J. Circuits Syst., 2021
Scalable Hardware Architecture for Invertible Logic with Sparse Hamiltonian Matrices.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2021
High Convergence Rates of CMOS Invertible Logic Circuits Based on Many-Body Hamiltonians.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
2020
High-Throughput/Low-Energy MTJ-Based True Random Number Generator Using a Multi-Voltage/Current Converter.
IEEE Trans. Very Large Scale Integr. Syst., 2020
IEEE Trans. Very Large Scale Integr. Syst., 2020
IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020
Fast Hardware-based Learning Algorithm for Binarized Perceptrons using CMOS Invertible Logic.
FLAP, 2020
FLAP, 2020
FLAP, 2020
Training Hardware for Binarized Convolutional Neural Network Based on CMOS Invertible Logic.
IEEE Access, 2020
Design of an Energy-Efficient True Random Number Generator Based on Triple Read-Write Data-Stream Multiplexing of MTJ Devices.
Proceedings of the 18th IEEE International New Circuits and Systems Conference, 2020
2019
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
FPGA Implementation of Binarized Perceptron Learning Hardware Using CMOS Invertible Logic.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
2018
A Generalized Stochastic Implementation of the Disparity Energy Model for Depth Perception.
J. Signal Process. Syst., 2018
IEEE Trans. Very Large Scale Integr. Syst., 2018
MTJ-based asynchronous circuits for Re-initialization free computing against power failures.
Microelectron. J., 2018
An Accuracy/Energy-Flexible Configurable Gabor-Filter Chip Based on Stochastic Computation With Dynamic Voltage-Frequency-Length Scaling.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018
Design of a Low-Power MTJ-Based True Random Number Generator Using a Multi-voltage/Current Converter.
Proceedings of the 48th IEEE International Symposium on Multiple-Valued Logic, 2018
High-Precision Stochastic State-Space Digital Filters Based on Minimum Roundoff Noise Structure.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018
2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
Sudden Power-Outage Resilient In-Processor Checkpointing for Energy-Harvesting Nonvolatile Processors.
IEEE Trans. Emerg. Top. Comput., 2017
High-Accuracy and Area-Efficient Stochastic FIR Digital Filters Based on Hybrid Computation.
IEICE Trans. Inf. Syst., 2017
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017
Proceedings of the 47th IEEE International Symposium on Multiple-Valued Logic, 2017
Proceedings of the 2017 IEEE Global Conference on Signal and Information Processing, 2017
Accuracy/energy-flexible stochastic configurable 2D Gabor filter with instant-on capability.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017
Three-terminal MTJ-based nonvolatile logic circuits with self-terminated writing mechanism for ultra-low-power VLSI processor.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
2016
Proc. IEEE, 2016
J. Multiple Valued Log. Soft Comput., 2016
Hardware Implementation of Associative Memories Based on Multiple-Valued Sparse Clustered Networks.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016
Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016
Proceedings of the 9th International Symposium on Turbo Codes and Iterative Information Processing, 2016
Proceedings of the 46th IEEE International Symposium on Multiple-Valued Logic, 2016
Proceedings of the 2016 IEEE International Conference on Acoustics, 2016
2015
Algorithm and Architecture for a Low-Power Content-Addressable Memory Based on Sparse Clustered Networks.
IEEE Trans. Very Large Scale Integr. Syst., 2015
Proceedings of the 2015 IEEE Workshop on Signal Processing Systems, 2015
Design of an STT-MTJ based true random number generator using digitally controlled probability-locked loop.
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015
A sudden power-outage resilient nonvolatile microprocessor for immediate system recovery.
Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015
Proceedings of the 2015 IEEE International Symposium on Multiple-Valued Logic, 2015
Proceedings of the 2015 IEEE International Conference on Digital Signal Processing, 2015
Spintronics-based nonvolatile logic-in-memory architecture towards an ultra-low-power and highly reliable VLSI computing paradigm.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
2014
Clockless Stochastic Decoding of Low-Density Parity-Check Codes: Architecture and Simulation Model.
J. Signal Process. Syst., 2014
Algorithm and Architecture of Fully-Parallel Associative Memories Based on Sparse Clustered Networks.
J. Signal Process. Syst., 2014
High-Throughput Low-Energy Self-Timed CAM Based on Reordered Overlapped Search Mechanism.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
IEEE Trans. Computers, 2014
High-Throughput Partially Parallel Inter-Chip Link Architecture for Asynchronous Multi-Chip NoCs.
IEICE Trans. Inf. Syst., 2014
IEICE Trans. Inf. Syst., 2014
Soft-error tolerant transistor/magnetic-tunnel-junction hybrid non-volatile C-element.
IEICE Electron. Express, 2014
A Nonvolatile Associative Memory-Based Context-Driven Search Engine Using 90 nm CMOS/MTJ-Hybrid Logic-in-Memory Architecture.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2014
Algorithm and architecture for a multiple-field context-driven search engine using fully-parallel clustered associative memories.
Proceedings of the 2014 IEEE Workshop on Signal Processing Systems, 2014
Design of a soft-error tolerant 9-transistor/6-magnetic-tunnel-junction hybrid cell based nonvolatile TCAM.
Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2014
Proceedings of the IEEE 44th International Symposium on Multiple-Valued Logic, 2014
Proceedings of the IEEE 44th International Symposium on Multiple-Valued Logic, 2014
A Compact Soft-Error Tolerant Asynchronous TCAM Based on a Transistor/Magnetic-Tunnel-Junction Hybrid Dual-Rail Word Structure.
Proceedings of the 20th IEEE International Symposium on Asynchronous Circuits and Systems, 2014
Highly reliable single-ended current-mode circuit for an inter-chip asynchronous communication link.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014
2013
Open-Fault Resilient Multiple-Valued Codes for Reliable Asynchronous Global Communication Links.
IEICE Trans. Inf. Syst., 2013
IEICE Electron. Express, 2013
Lowering Error Floors in Stochastic Decoding of LDPC Codes Based on Wire-Delay Dependent Asynchronous Updating.
Proceedings of the 43rd IEEE International Symposium on Multiple-Valued Logic, 2013
Proceedings of the IEEE International Conference on Acoustics, 2013
Proceedings of the IEEE Global Conference on Signal and Information Processing, 2013
Low-power area-efficient large-scale IP lookup engine based on binary-weighted clustered networks.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
A Low-Energy Variation-Tolerant Asynchronous TCAM for Network Intrusion Detection Systems.
Proceedings of the 19th IEEE International Symposium on Asynchronous Circuits and Systems, 2013
Proceedings of the 24th International Conference on Application-Specific Systems, 2013
2012
Long-Range Asynchronous On-Chip Link Based on Multiple-Valued Single-Track Signaling.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012
Proceedings of the 2012 IEEE Workshop on Signal Processing Systems, 2012
Proceedings of the IEEE 18th Pacific Rim International Symposium on Dependable Computing, 2012
Proceedings of the 42nd IEEE International Symposium on Multiple-Valued Logic, 2012
Systematic Coding Schemes for Low-Power Multiple-Valued Current-Mode Asynchronous Communication Links.
Proceedings of the 42nd IEEE International Symposium on Multiple-Valued Logic, 2012
Architecture and implementation of an associative memory using sparse clustered networks.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
High-Throughput Low-Energy Content-Addressable Memory Based on Self-Timed Overlapped Search Mechanism.
Proceedings of the 18th IEEE International Symposium on Asynchronous Circuits and Systems, 2012
2011
IEEE Trans. Circuits Syst. I Regul. Pap., 2011
Complementary Multiple-Valued Encoding Scheme for Interconnect-Fault-Resilient Bidirectional Asynchronous Links.
Proceedings of the 41st IEEE International Symposium on Multiple-Valued Logic, 2011
Adjacent-State monitoring based fine-grained power-gating scheme for a low-power asynchronous pipelined system.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Interconnect-fault-resilient delay-insensitive asynchronous communication link based on current-flow monitoring.
Proceedings of the Design, Automation and Test in Europe, 2011
2010
IEEE Trans. Very Large Scale Integr. Syst., 2010
Highly Reliable Multiple-Valued One-Phase Signalling for an Asynchronous On-Chip Communication Link.
IEICE Trans. Inf. Syst., 2010
Proceedings of the VLSI 2010 Annual Symposium - Selected papers, 2010
One-Color Two-Phase Asynchronous Communication Links Based on Multiple-Valued Simultaneous Control.
Proceedings of the 40th IEEE International Symposium on Multiple-Valued Logic, 2010
High-throughput protocol converter based on an independent encoding/decoding scheme for asynchronous Network-on-Chip.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
2009
High-Throughput Bit-Serial LDPC Decoder LSI Based on Multiple-Valued Asynchronous Interleaving.
IEICE Trans. Electron., 2009
Robust Multiple-Valued Current-Mode Circuit Components Based on Adaptive Reference-Voltage Control.
Proceedings of the ISMVL 2009, 2009
High-performance Asynchronous Intra-chip Communication Link based on a Multiple-valued Current-mode Single-track Scheme.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
2008
Power-Aware Asynchronous Peer-to-Peer Duplex Communication System Based on Multiple-Valued One-Phase Signaling.
IEICE Trans. Electron., 2008
High-Speed Timing Verification Scheme Using Delay Tables for a Large-Scaled Multiple-Valued Current-Mode Circuit.
Proceedings of the 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 2008
2006
Design and Evaluation of a NULL-Convention Circuit Based on Dual-Rail Current-Mode Differential Logic.
IEICE Trans. Electron., 2006
2005
Multiple-Valued Duplex Asynchronous Data Transfer Scheme for Interleaving in LDPC Decoders.
Proceedings of the 35th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2005), 2005