Masanori Natsui
Orcid: 0000-0001-7424-4663
According to our database1,
Masanori Natsui
authored at least 50 papers
between 2001 and 2023.
Collaborative distances:
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Bibliography
2023
Design of an Error-Tolerant Nonvolatile Register for Energy-Aware Intermittent Computing.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023
Proceedings of the 53rd IEEE International Symposium on Multiple-Valued Logic, 2023
High-Performance/Low-Area Power-Gating Switch Linear Array for Energy-Efficient LSIs with an Optimum Switch-Timing Control.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Error-Sensitivity-Aware Write-Energy Optimization for an MTJ-Based Binarized Neural Network.
Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023
2022
Energy-Efficient Nonvolatile RISC-V CPU with a Custom Instruction-Controlled Accelerator.
Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022
2021
Dual-Port SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations Under Field-Assistance-Free Condition.
IEEE J. Solid State Circuits, 2021
2020
Dual-Port Field-Free SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations under 55-nm CMOS Technology and 1.2-V Supply Voltage.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
2019
A 47.14-µW 200-MHz MOS/MTJ-Hybrid Nonvolatile Microcontroller Unit Embedding STT-MRAM and FPGA for IoT Applications.
IEEE J. Solid State Circuits, 2019
An FPGA-Accelerated Fully Nonvolatile Microcontroller Unit for Sensor-Node Applications in 40nm CMOS/MTJ-Hybrid Technology Achieving 47.14μW Operation at 200MHz.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
Design of a Current-Mode Linear-Sum-Based Bitcounting Circuit with an MTJ-Based Compensator for Binarized Neural Networks.
Proceedings of the 2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL), 2019
2018
Microelectron. J., 2018
Systematic Intrusion Detection Technique for an In-vehicle Network Based on Time-Series Feature Extraction.
Proceedings of the 48th IEEE International Symposium on Multiple-Valued Logic, 2018
2017
Three-terminal MTJ-based nonvolatile logic circuits with self-terminated writing mechanism for ultra-low-power VLSI processor.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
2016
Proc. IEEE, 2016
A study of a top-down error correction technique using Recurrent-Neural-Network-based learning.
Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016
Context-Based Error Correction Scheme Using Recurrent Neural Network for Resilient and Efficient Intra-Chip Data Transmission.
Proceedings of the 46th IEEE International Symposium on Multiple-Valued Logic, 2016
Stochastic behavior-considered VLSI CAD environment for MTJ/MOS-hybrid microprocessor design.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
2015
Nonvolatile Logic-in-Memory LSI Using Cycle-Based Power Gating and its Application to Motion-Vector Prediction.
IEEE J. Solid State Circuits, 2015
Fabrication of a 3000-6-input-LUTs embedded and block-level power-gated nonvolatile FPGA chip using p-MTJ-based logic-in-memory structure.
Proceedings of the Symposium on VLSI Circuits, 2015
Write-Operation Frequency Reduction for Nonvoratile Logic LSI with a Short Break-Even Time.
Proceedings of the 2015 IEEE International Symposium on Multiple-Valued Logic, 2015
Spintronics-based nonvolatile logic-in-memory architecture towards an ultra-low-power and highly reliable VLSI computing paradigm.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
2014
A compact low-power nonvolatile flip-flop using domain-wall-motion-device-based single-ended structure.
IEICE Electron. Express, 2014
Fabrication of a MTJ-based multilevel resistor towards process-variaton-resilient logic LSI.
Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014
Proceedings of the IEEE 44th International Symposium on Multiple-Valued Logic, 2014
2013
Design of Process-Variation-Resilient Analog Basic Components Using Magnetic-Tunnel-Junction Devices.
J. Multiple Valued Log. Soft Comput., 2013
Fabrication of a magnetic tunnel junction-based 240-tile nonvolatile field-programmable gate array chip skipping wasted write operations for greedy power-reduced logic applications.
IEICE Electron. Express, 2013
Nonvolatile logic-in-memory array processor in 90nm MTJ/MOS achieving 75% leakage reduction using cycle-based power gating.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
Proceedings of the 43rd IEEE International Symposium on Multiple-Valued Logic, 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
2012
Low-Energy Pipelined Multiple-Valued Current-Mode Circuit Based on Current-Level Control Technique.
J. Multiple Valued Log. Soft Comput., 2012
Scalable serial-configuration scheme for MTJ/MOS-hybrid variation-resilient VLSI system.
Proceedings of the 10th IEEE International NEWCAS Conference, 2012
Area-efficient LUT circuit design based on asymmetry of MTJ's current switching for a nonvolatile FPGA.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012
Proceedings of the 42nd IEEE International Symposium on Multiple-Valued Logic, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Implementation of a perpendicular MTJ-based read-disturb-tolerant 2T-2R nonvolatile TCAM based on a reversed current reading scheme.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
2011
Design Optimization of High-Speed and Low-Power Operational Transconductance Amplifier Using <i>g<sub>m</sub></i>/<i>I<sub>D</sub></i> Lookup Table Methodology.
IEICE Trans. Electron., 2011
Design of a Low-Energy Nonvolatile Fully-Parallel Ternary CAM Using a Two-Level Segmented Match-Line Scheme.
Proceedings of the 41st IEEE International Symposium on Multiple-Valued Logic, 2011
2010
Energy-Aware Multiple-Valued Current-Mode Sequential Circuits Using a Completion-Detection Scheme.
IEICE Trans. Inf. Syst., 2010
Low-Energy Pipelined Multiple-Valued Current-Mode Circuit with 8-Level Static Current-Source Control.
Proceedings of the 40th IEEE International Symposium on Multiple-Valued Logic, 2010
2009
Timing-Variation-Aware Multiple-Valued Current-Mode Circuit for a Low-Power Pipelined System.
Proceedings of the ISMVL 2009, 2009
2008
Automated Sizing of Analog Circuits based on Genetic Algorithm with Parameter Orthogonalization Procedure.
Proceedings of the ICINCO 2008, 2008
2007
Synthesis of current mirrors based on evolutionary graph generation with transmigration capability.
IEICE Electron. Express, 2007
2006
Pitch estimation of difficult polyphony sounds overlapping some frequency components.
Proceedings of the ICINCO 2006, 2006
GA-based approach to pitch recognition of musical consonance.
Proceedings of the ICINCO 2006, 2006
2005
J. Multiple Valued Log. Soft Comput., 2005
2004
Proceedings of the Parallel Problem Solving from Nature, 2004
2003
VLSI circuit design using an object-oriented framework of evolutionary graph generation system.
Proceedings of the IEEE Congress on Evolutionary Computation, 2003
2002
Parallel Evolutionary Graph Generation with Terminal-Color Constraint and Its Application to Current-Mode Logic Circuit Design.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002
Parallel Evolutionary Graph Synthesis on a PC Cluster and Its Application to Multiple-Valued Circuit Synthesis.
Proceedings of the 32nd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2002), 2002
2001
Synthesis of Multiple-Valued Arithmetic Circuits Using Evolutionary Graph Generation.
Proceedings of the 31st IEEE International Symposium on Multiple-Valued Logic, 2001