Hiroyuki Kurino

According to our database, Hiroyuki Kurino authored at least 7 papers between 1998 and 2005.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2005

Dynamic Multi-Context Reconfiguration Scheme for Reconfigurable Parallel Image Processing System with Three Dimensional Structure.

Takeaki Sugimura, Yuta Konishi, Yoshihiro Nakatani, Takafumi Fukushima, Hiroyuki Kurino, Mitsumasa Koyanagi

Proceedings of the 18th International Conference on Architecture of Computing Systems, 2005

2004

Design and Evaluation of a Novel Real-Shared Cache Module for High Performance Parallel Processor Chip.

Zhe Liu, JeoungChill Shim, Hiroyuki Kurino, Mitsumasa Koyanagi

Proceedings of the Parallel and Distributed Computing: Applications and Technologies, 2004

Design of A Novel Real-Shared Memory Module for High Performance Parallel Processor System with Shared Memory.

Zhe Liu, JeoungChill Shim, Hiroyuki Kurino, Mitsumasa Koyanagi

Proceedings of the 18th International Conference on Advanced Information Networking and Applications (AINA 2004), 2004

2003

Parallel image processing field programmable gate array for real time image processing system.

Takeaki Sugimura, JeoungChill Shim, Hiroyuki Kurino, Mitsumasa Koyanagi

Proceedings of the 2003 IEEE International Conference on Field-Programmable Technology, 2003

2000

Smart Vision Chip Fabricated Using Three Dimensional Integration Technology.

Hiroyuki Kurino, Masaki Nakagawa, Kang Wook Lee, Tomonori Nakamura, Yuusuke Yamada, Ki Tae Park, Mitsumasa Koyanagi

Proceedings of the Advances in Neural Information Processing Systems 13, 2000

1998

Future system-on-silicon LSI chips.

Mitsumasa Koyanagi, Hiroyuki Kurino, Kang Wook Lee, Katsuyuki Sakuma, Nobuaki Miyakawa, Hikotaro Itani

IEEE Micro, 1998

A New Multiport Memory for High Performance Parallel Processor System with Shared Memory.

Keiichi Hirano, Taizou Ono, Hiroyuki Kurino, Mitsumasa Koyanagi

Proceedings of the ASP-DAC '98, 1998