William C. Miller

IEEE Trans. Instrum. Meas., 2010

2009

A Delay Generation Technique for Narrow Time Interval Measurement.

[BibT_eX]

[DOI]

IEEE Trans. Instrum. Meas., 2009

2007

Test and Measurement of Analog and RF Cores in Mixed-Signal SoC Environment.

[BibT_eX]

[DOI]

Rashid Rashidzadeh

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

2005

Efficient Techniques for Binary-to-Multidigit Multidimensional Logarithmic Number System Conversion Using Range-Addressable Look-Up Tables.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2005

A Low-Power Two-Digit Multi-dimensional Logarithmic Number System Filterbank Architecture for a Digital Hearing Aid.

[BibT_eX]

[DOI]

EURASIP J. Adv. Signal Process., 2005

DBNS addition using cellular neural networks.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Power and delay analysis of 4: 2 compressor cells.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A New Method of Electrostatic Force Modeling for MEMS Sensors and Actuators.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Conference on MEMS, 2005

2004

A Sigma-Delta Modulator for Digital Hearing Instruments Using 0.18µm CMOS Technology.

[BibT_eX]

[DOI]

Iman Y. Taha

Proceedings of the 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'04), 2004

Ultra Low Noise Signed Digit Arithmetic using Cellular Neural Networks.

[BibT_eX]

[DOI]

Y. Ibrahim

Proceedings of the 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'04), 2004

Electrical connectivity analysis of a MEMS micropackage.

[BibT_eX]

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

The Concept of a 3-D Cubic Acoustical Sensor Microarray Cluster for Use in a Hearing Instrument.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Conference on MEMS, 2004

2003

A Feed-Forward Time-Multiplexed Neural Network with Mixed-Signal Neuron-Synapse Arrays.

[BibT_eX]

Mitra Mirhassani

Proceedings of the International Conference on VLSI, 2003

A Low-Voltage Low-Power Digital-Audio Sigma-Delta Modulator in 0.18-µm CMOS.

[BibT_eX]

Jiyi Gu

Proceedings of the International Conference on VLSI, 2003

The Application of 2D Algebraic Integer Encoding to a DCT IP Core.

[BibT_eX]

[DOI]

Proceedings of the 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 30 June, 2003

A tester-on-chip implementation in 0.18µ CMOS utilizing a MEMS interface.

[BibT_eX]

[DOI]

Rashid Rashidzadeh

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A MEMS custom micropackaging solution.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Nonlinear Effects in MEMS Capacitive Microphone Design.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Conference on MEMS, 2003

2002

A New Algorithm for the Elimination of Common Subexpressions in Hardware Implementation of Digital Filters by Using Genetic Programming.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 2002

A MEMS socket system for high density SoC interconnection.

[BibT_eX]

[DOI]

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

A B-s complement continuous valued digit adder.

[BibT_eX]

[DOI]

Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

Multi-features and Multi-stages RBF Neural Network Classifier with Fuzzy Integral in Human Face Recognition.

[BibT_eX]

Javad Haddadnia

Proceedings of the International Conference on Artificial Intelligence, 2002

Efficient Conversion From Binary to Multi-Digit Multi-Dimensional Logarithmic Number Systems Using Arrays of Range Addressable Look-Up Tables.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on Application-Specific Systems, 2002

2001

A novel approach based on genetic algorithm for pipelining of recursive filters.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

A MEMS implementation of an acoustical sensor array.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

The Use of the Multi-Dimensional Logarithmic Number System in DSP Applications.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE Symposium on Computer Arithmetic (Arith-15 2001), 2001

2000

Complexity and Fast Algorithms for Multiexponentiations.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2000

Design of Stable 3D Recursive Digital Filters Using 3-Variable Very Strictly Hurwitz Polynomial.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2000

A MEMS micromagnetic actuator for use in a bionic interface.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1999

Theory and Applications of the Double-Base Number System.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1999

Design of 1-D FIR filters with genetic algorithms.

[BibT_eX]

[DOI]

Proceedings of the ISSPA '99. Proceedings of the Fifth International Symposium on Signal Processing and its Applications, 1999

An in-the-loop training method for VLSI neural networks.

[BibT_eX]

[DOI]

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Designing FIR filters with enhanced Fermat ALUs.

[BibT_eX]

[DOI]

M. Shahkarami

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Design of 1-D FIR filters with genetic algorithms.

[BibT_eX]

[DOI]

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

A hybrid DBNS processor for DSP computation.

[BibT_eX]

[DOI]

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Sensitivity study and improvements on a nonlinear resistive-type neuron circuit.

[BibT_eX]

[DOI]

Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

1998

A residue number system implementation of real orthogonal transforms.

[BibT_eX]

[DOI]

IEEE Trans. Signal Process., 1998

Digital Arithmetic Using Analog Cellular Neural Networks.

[BibT_eX]

[DOI]

Saeid Sadeghi-Emamchaie

J. Circuits Syst. Comput., 1998

Neural Network Integrated Circuits with Single-Block Mixed Signal Arrays.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 1998

A Low-Variation Nonlinear Neuron Circuit.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 1998

An Algorithm for Modular Exponentiation.

[BibT_eX]

[DOI]

Inf. Process. Lett., 1998

A new DCT algorithm based on encoding algebraic integers.

[BibT_eX]

[DOI]

Proceedings of the 1998 IEEE International Conference on Acoustics, 1998

Digital Arithmetic Using Analog Arrays.

[BibT_eX]

[DOI]

Saeid Sadeghi-Emamchaie

Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998

1997

Fast adders using enhanced multiple-output domino logic.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 1997

Algorithms for Multi-Exponentiation Based on Complex Arithmetic.

[BibT_eX]

[DOI]

Proceedings of the 13th Symposium on Computer Arithmetic (ARITH-13 '97), 1997

1996

An efficient tree architecture for modulo 2<sup><i>n</i></sup>+1 multiplication.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 1996

On computing Chebyshev optimal nonuniform interpolation.

[BibT_eX]

[DOI]

Signal Process., 1996

A modular architecture for hybrid VLSI neural networks and its application in a smart photosensor.

[BibT_eX]

[DOI]

Proceedings of International Conference on Neural Networks (ICNN'96), 1996

Design and VLSI Implementation of a Unified Synapse-Neuron Architecture.

[BibT_eX]

[DOI]

Proceedings of the 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), 1996

1995

A New Design Technique for Column Compression Multipliers.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1995

An array processor for inner product computations using a Fermat number ALU.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Application Specific Array Processors (ASAP'95), 1995

1994

Dynamic computational blocks for bit-level systolic arrays.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, January, 1994

Comments on "On asymmetrical performance of discrete cosine transform".

[BibT_eX]

[DOI]

IEEE Trans. Signal Process., 1994

Solving linear algebraic equations without error.

[BibT_eX]

[DOI]

IEEE Signal Process. Lett., 1994

Recursive algorithms for the forward and inverse discrete cosine transform with arbitrary length.

[BibT_eX]

[DOI]

IEEE Signal Process. Lett., 1994

The generalized discrete W transform and its application to interpolation.

[BibT_eX]

[DOI]

Signal Process., 1994

Current Input TSPC Latch for High Speed, Complex Switching Trees.

[BibT_eX]

[DOI]

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Area-Time Analysis of Carry Lookahead Adders Using Enhanced Multiple Output Domino Logic.

[BibT_eX]

[DOI]

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

A regular recursive algorithm for the discrete sine transform.

[BibT_eX]

[DOI]

Proceedings of ICASSP '94: IEEE International Conference on Acoustics, 1994

1993

An improved digit-reversal permutation algorithm.

[BibT_eX]

[DOI]

Xiangui Yu

Nan K. Loh

Signal Process., 1993

VLSI implementations of number theoretic techniques in signal processing.

[BibT_eX]

[DOI]

Neil M. Wigley

Integr., 1993

A new algorithm for training multilayer feedforward neural networks.

[BibT_eX]

Xiangui Yu

Nan K. Loh

Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

New Concepts for the Design of Carry Lookahaead Adders.

[BibT_eX]

Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

A new acceleration technique for the backpropagation algorithm.

[BibT_eX]

[DOI]

Xiangui Yu

Nan K. Loh

Proceedings of International Conference on Neural Networks (ICNN'88), San Francisco, CA, USA, March 28, 1993

Integer mapping architectures for the polynomial ring engine.

[BibT_eX]

[DOI]

Proceedings of the 11th Symposium on Computer Arithmetic, 29 June, 1993

1991

Arithmetic for digital neural networks.

[BibT_eX]

[DOI]

David Zhang

Earl E. Swartzlander Jr.

Proceedings of the 10th IEEE Symposium on Computer Arithmetic, 1991

Small moduli replications in the MRRNS.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE Symposium on Computer Arithmetic, 1991

1990

A low-overhead scheme for testing a bit-level finite ring systolic array.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 1990

1989

An efficient bit-level systolic cell design for finite ring digital signal processing applications.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 1989

1988

High-speed signal processing using systolic arrays over finite rings.

[BibT_eX]

[DOI]

Majid Taheri

IEEE J. Sel. Areas Commun., 1988

1987

Systolic ROM arrays for implementing RNS FIR filters.

[BibT_eX]

[DOI]

Majid Taheri

Proceedings of the IEEE International Conference on Acoustics, 1987

VLSI Modular architectures for complex digital signal processing applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 1987

Implementation of the generalized FIR filter structure using the residue arithmetic.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 1987

1986

Complex digital signal processing using quadratic residue number systems.

[BibT_eX]

[DOI]

IEEE Trans. Acoust. Speech Signal Process., 1986

The implementation of the generalized Lagrange FIR filter structure defined over finite fields or rings.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 1986

Computation of complex number theoretic transforms using quadratic residue number systems.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 1986

A VLSI array for computing the DFT based on RNS.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 1986

VLSI Implementation of Complex Digitial Signal Processing Structures.

[BibT_eX]

Proceedings of the Intelligent Autonomous Systems, 1986

1985

Software techniques for programming a general purpose data flow signal processor.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 1985

An efficient VLSI adder for DSP architectures based on RNS.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 1985

A VLSI implementation of an FFT/NTT computational unit.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 1985

1984

A VLSI model for residue number system architectures.

[BibT_eX]

[DOI]

Integr., 1984

A real time general purpose signal processor.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 1984

A systolic (VLSI) array using RNS for digital signal processing applications.

[BibT_eX]

[DOI]

Proceedings of the ACM 12th annual computer science conference on SIGCSE symposium, 1984

1983

Processor Architectures for Two-Dimensional Convolvers Using a Single Multiplexed Computational Element with Finite Field Arithmetic.

[BibT_eX]

[DOI]

Hari K. Nagpal

IEEE Trans. Computers, 1983

An area-time efficient NMOS adder.

[BibT_eX]

[DOI]

Integr., 1983

Models for VLSI implementation of residue number system arithmetic modules.

[BibT_eX]

[DOI]

Proceedings of the 6th IEEE Symposium on Computer Arithmetic, 1983

1982

Memory architecture of a video-rate image convolver.

[BibT_eX]

[DOI]

Hari K. Nagpal

Proceedings of the IEEE International Conference on Acoustics, 1982

1981

A two-dimensional finite field processor for image filtering.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 1981

1980

A hardware realization of an NTT convolver using ROM arrays.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 1980

1979

Implementation of FFT Structures Using the Residue Number System.

[BibT_eX]

[DOI]

Ben-Dau Tseng

IEEE Trans. Computers, 1979

1978

On Computing the Discrete Cosine Transform.

[BibT_eX]

[DOI]

Ben-Dau Tseng

IEEE Trans. Computers, 1978

An error anaylsis of a FFT implementation using the residue number system.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 1978

Application of the residue number system to computer processing of digital signals.

[BibT_eX]

[DOI]