Hoyoung Yoo

According to our database1, Hoyoung Yoo authored at least 18 papers between 2011 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

Online presence:

On csauthors.net:

Bibliography

2019
On-demand Syndrome Calculation for BCH decoding.
Proceedings of the International Conference on Electronics, Information, and Communication, 2019

2018
Resource usage of LTE networks for machine-to-Machine group communications: Modeling and analysis.
Comput. Electr. Eng., 2018

Hybrid Decoding for Polar Codes.
Proceedings of the International SoC Design Conference, 2018

2016
Energy-Efficient Floating-Point MFCC Extraction Architecture for Speech Recognition Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Low-Power Parallel Chien Search Architecture Using a Two-Step Approach.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

Efficient Sorting Architecture for Successive-Cancellation-List Decoding of Polar Codes.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

Efficient Pruning for Successive-Cancellation Decoding of Polar Codes.
IEEE Commun. Lett., 2016

2015
Partially Parallel Encoder Architecture for Long Polar Codes.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

Efficient Parallel Architecture for Linear Feedback Shift Registers.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

2014
High-Throughput and Low-Complexity BCH Decoding Architecture for Solid-State Drives.
IEEE Trans. Very Large Scale Integr. Syst., 2014

7.3 Gb/s universal BCH encoder and decoder for SSD controllers.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
Area-Efficient Multimode Encoding Architecture for Long BCH Codes.
IEEE Trans. Circuits Syst. II Express Briefs, 2013

A 2.74-pJ/bit, 17.7-Gb/s Iterative Concatenated-BCH Decoder in 65-nm CMOS for NAND Flash Memory.
IEEE J. Solid State Circuits, 2013

A 3Gb/s 2.08mm<sup>2</sup> 100b error-correcting BCH decoder in 0.13µm CMOS process.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
6.4Gb/s multi-threaded BCH encoder and decoder for multi-channel SSD controllers.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

Low-latency area-efficient decoding architecture for shortened reed-solomon codes.
Proceedings of the International SoC Design Conference, 2012

Small-area parallel syndrome calculation for strong BCH decoding.
Proceedings of the 2012 IEEE International Conference on Acoustics, 2012

2011
Low-Complexity Parallel Chien Search Structure Using Two-Dimensional Optimization.
IEEE Trans. Circuits Syst. II Express Briefs, 2011


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