Hoyoung Yoo

According to our database, Hoyoung Yoo authored at least 18 papers between 2011 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2019

On-demand Syndrome Calculation for BCH decoding.

Hyeonkyu Kim, Soyeon Choi, Hoyoung Yoo

Proceedings of the International Conference on Electronics, Information, and Communication, 2019

2018

Resource usage of LTE networks for machine-to-Machine group communications: Modeling and analysis.

Eunmi Chu, Hoyoung Yoo, Bang Chul Jung

Comput. Electr. Eng., 2018

Hybrid Decoding for Polar Codes.

Soyeon Choi, Hoyoung Yoo

Proceedings of the International SoC Design Conference, 2018

2016

Energy-Efficient Floating-Point MFCC Extraction Architecture for Speech Recognition Systems.

Jihyuck Jo, Hoyoung Yoo, In-Cheol Park

IEEE Trans. Very Large Scale Integr. Syst., 2016

Low-Power Parallel Chien Search Architecture Using a Two-Step Approach.

Hoyoung Yoo, Youngjoo Lee, In-Cheol Park

IEEE Trans. Circuits Syst. II Express Briefs, 2016

Efficient Sorting Architecture for Successive-Cancellation-List Decoding of Polar Codes.

Byeong Yong Kong, Hoyoung Yoo, In-Cheol Park

IEEE Trans. Circuits Syst. II Express Briefs, 2016

Efficient Pruning for Successive-Cancellation Decoding of Polar Codes.

Hoyoung Yoo, In-Cheol Park

IEEE Commun. Lett., 2016

2015

Partially Parallel Encoder Architecture for Long Polar Codes.

Hoyoung Yoo, In-Cheol Park

IEEE Trans. Circuits Syst. II Express Briefs, 2015

Efficient Parallel Architecture for Linear Feedback Shift Registers.

Jaehwan Jung, Hoyoung Yoo, Youngjoo Lee, In-Cheol Park

IEEE Trans. Circuits Syst. II Express Briefs, 2015

2014

High-Throughput and Low-Complexity BCH Decoding Architecture for Solid-State Drives.

Youngjoo Lee, Hoyoung Yoo, Injae Yoo, In-Cheol Park

IEEE Trans. Very Large Scale Integr. Syst., 2014

7.3 Gb/s universal BCH encoder and decoder for SSD controllers.

Hoyoung Yoo, Youngjoo Lee, In-Cheol Park

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013

Area-Efficient Multimode Encoding Architecture for Long BCH Codes.

Hoyoung Yoo, Jaehwan Jung, Jihyuck Jo, In-Cheol Park

IEEE Trans. Circuits Syst. II Express Briefs, 2013

A 2.74-pJ/bit, 17.7-Gb/s Iterative Concatenated-BCH Decoder in 65-nm CMOS for NAND Flash Memory.

Youngjoo Lee, Hoyoung Yoo, Jaehwan Jung, Jihyuck Jo, In-Cheol Park

IEEE J. Solid State Circuits, 2013

A 3Gb/s 2.08mm² 100b error-correcting BCH decoder in 0.13µm CMOS process.

Youngjoo Lee, Hoyoung Yoo, In-Cheol Park

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012

6.4Gb/s multi-threaded BCH encoder and decoder for multi-channel SSD controllers.

Youngjoo Lee, Hoyoung Yoo, Injae Yoo, In-Cheol Park

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

Low-latency area-efficient decoding architecture for shortened reed-solomon codes.

Hoyoung Yoo, Youngjoo Lee, In-Cheol Park

Proceedings of the International SoC Design Conference, 2012

Small-area parallel syndrome calculation for strong BCH decoding.

Youngjoo Lee, Hoyoung Yoo, In-Cheol Park

Proceedings of the 2012 IEEE International Conference on Acoustics, 2012

2011

Low-Complexity Parallel Chien Search Structure Using Two-Dimensional Optimization.

Youngjoo Lee, Hoyoung Yoo, In-Cheol Park

IEEE Trans. Circuits Syst. II Express Briefs, 2011