Dongyun Kam

According to our database, Dongyun Kam authored at least 14 papers between 2019 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

2.8 A 21.9ns 15.7 Gbps/mm² (128,15) BOSS FEC Decoder for 5G/6G URLLC Applications.

Dongyun Kam, Sangbu Yun, Jeongwon Choe, Zhengya Zhang, Namyoon Lee, Youngjoo Lee

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2023

Low-Latency SCL Polar Decoder Architecture Using Overlapped Pruning Operations.

Dongyun Kam, Byeong Yong Kong, Youngjoo Lee

IEEE Trans. Circuits Syst. I Regul. Pap., March, 2023

Energy-Efficient RISC-V-Based Vector Processor for Cache-Aware Structurally-Pruned Transformers.

Jung Gyu Min, Dongyun Kam, Younghoon Byun, Gunho Park, Youngjoo Lee

Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023

GROW: A Row-Stationary Sparse-Dense GEMM Accelerator for Memory-Efficient Graph Convolutional Neural Networks.

Ranggi Hwang, Minhoo Kang, Jiwon Lee, Dongyun Kam, Youngjoo Lee, Minsoo Rhu

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023

2022

Low-Complexity and Low-Latency SVC Decoding Architecture Using Modified MAP-SP Algorithm.

Seungwoo Hong, Dongyun Kam, Sangbu Yun, Jeongwon Choe, Namyoon Lee, Youngjoo Lee

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Simplified Ordered Statistic Decoding for Short-Length Linear Block Codes.

Changhyeon Kim, Dongyun Kam, Seokki Kim, Giyoon Park, Youngjoo Lee

IEEE Commun. Lett., 2022

A 1.1μs 1.56Gb/s/mm² Cost-Efficient Large-List SCL Polar Decoder Using Fully-Reusable LLR Buffers in 28nm CMOS Technology.

Dongyun Kam, Byeong Yong Kong, Youngjoo Lee

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

Design and Evaluation Frameworks for Advanced RISC-based Ternary Processor.

Dongyun Kam, Jung Gyu Min, Jongho Yoon, Sunmean Kim, Seokhyeong Kang, Youngjoo Lee

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021

Ultralow-Latency Successive Cancellation Polar Decoding Architecture Using Tree-Level Parallelism.

Dongyun Kam, Hoyoung Yoo, Youngjoo Lee

IEEE Trans. Very Large Scale Integr. Syst., 2021

Low-Latency Polar Decoder Using Overlapped SCL Processing.

Dongyun Kam, Byeong Yong Kong, Youngjoo Lee

Proceedings of the IEEE International Conference on Acoustics, 2021

FPGA-Based Ordered Statistic Decoding Architecture for B5G/6G URLLC IIOT Networks.

Changhyeon Kim, Dongyoung Rim, Jeongwon Choe, Dongyun Kam, Giyoon Park, Seokki Kim, Youngjoo Lee

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021

2020

Ultra-Low-Latency LDPC Decoding Architecture using Reweighted Offset Min-Sum Algorithm.

Sangbu Yun, Dongyun Kam, Jeongwon Choe, Byeong Yong Kong, Youngjoo Lee

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019

Massive MIMO Systems With Low-Resolution ADCs: Baseband Energy Consumption vs. Symbol Detection Performance.

Seungsik Moon, In-Soo Kim, Dongyun Kam, Dong-Woo Jee, Junil Choi, Youngjoo Lee

IEEE Access, 2019

Ultra-Low-Latency Parallel SC Polar Decoding Architecture for 5G Wireless Communications.

Dongyun Kam, Youngjoo Lee

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019