Jihyuck Jo

According to our database1, Jihyuck Jo authored at least 7 papers between 2013 and 2018.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2018
Energy-Efficient Convolution Architecture Based on Rescheduled Dataflow.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

DSIP: A Scalable Inference Accelerator for Convolutional Neural Networks.
IEEE J. Solid State Circuits, 2018

2017
Low-Latency Low-Cost Architecture for Square and Cube Roots.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

2016
Energy-Efficient Floating-Point MFCC Extraction Architecture for Speech Recognition Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2016

2014
Low-Complexity Low-Latency Architecture for Matching of Data Encoded With Hard Systematic Error-Correcting Codes.
IEEE Trans. Very Large Scale Integr. Syst., 2014

2013
Area-Efficient Multimode Encoding Architecture for Long BCH Codes.
IEEE Trans. Circuits Syst. II Express Briefs, 2013

A 2.74-pJ/bit, 17.7-Gb/s Iterative Concatenated-BCH Decoder in 65-nm CMOS for NAND Flash Memory.
IEEE J. Solid State Circuits, 2013


  Loading...