Youngjoo Lee

IEEE Trans. Circuits Syst. I Regul. Pap., April, 2026

Machine Learning Assisted Tilt/Azimuth Estimation for Passive Stylus Pens Using Position-Based Model Selection.

[BibT_eX]

[DOI]

Junseo Jo

Hyungcheol Shin

IEEE Access, 2026

UniC-Vision: A 14.4Gb/s 7.3pJ/b Universal Vision Transformer OFDM Channel Estimation Accelerator for B5G/6G AI-RAN.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2026

Memory-Efficient Partially Self-Corrected Min-Sum LDPC Decoder for 5G NR Applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2026

2025

A Lightweight ML-Based ECG Classification System Using Self-Personalized Anomaly Detector.

[BibT_eX]

[DOI]

IEEE J. Biomed. Health Informatics, December, 2025

NMIX: NoC-Aware Mixed Precision Quantization for Energy-Efficient ML Accelerator.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, December, 2025

Hybrid Ordered Statistics Decoding of Short-Length BCH Codes for URLLC Systems: Theoretical Analysis and Decoder Implementation.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., November, 2025

Distinguishing Pathologic Gait in Older Adults Using Instrumented Insoles and Deep Neural Networks.

[BibT_eX]

[DOI]

IEEE J. Biomed. Health Informatics, July, 2025

Area-Efficient Non-Binary LDPC Decoder With Column-Wise Trellis Min-Max Algorithm.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, March, 2025

High-Throughput Software-Defined LDPC Encoder and Decoder With x86-Based Data-Level Parallelism.

[BibT_eX]

[DOI]

IEEE Trans. Veh. Technol., January, 2025

mDARTS: Searching ML-Based ECG Classifiers Against Membership Inference Attacks.

[BibT_eX]

[DOI]

Eun-Bin Park

IEEE J. Biomed. Health Informatics, January, 2025

Energy-Efficient Flexible RNS-CKKS Processor for FHE-Based Privacy-Preserving Computing.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, January, 2025

RISC-V Driven Orchestration of Vector Processing Units and eFlash Compute-in-Memory Arrays for Fast and Accurate Keyword Spotting.

[BibT_eX]

[DOI]

Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025

2024

A Design Framework for Cost-Efficient Sorters With Arbitrary Input/Output Constraints.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., December, 2024

A Dual-Precision and Low-Power CNN Inference Engine Using a Heterogeneous Processing-in-Memory Architecture.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., December, 2024

Hard-Decision SCL Polar Decoder With Weighted Pruning Operation for Storage Applications.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, September, 2024

Multi-Group Multicasting Systems Using Multiple RISs.

[BibT_eX]

[DOI]

IEEE Trans. Wirel. Commun., August, 2024

A 43.9 μs IRS Controller SoC With Grid-Based Phase-Shift Optimization in 28 nm CMOS Technology for Next- Generation Communication.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., July, 2024

Intelligent MIMO Detection With Momentum-Induced Unfolded Layers.

[BibT_eX]

[DOI]

IEEE Wirel. Commun. Lett., March, 2024

2.8 A 21.9ns 15.7 Gbps/mm² (128,15) BOSS FEC Decoder for 5G/6G URLLC Applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

Constrained Sorter Design using Zero-One Principle.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

Partially-Structured Transformer Pruning with Patch-Limited XOR-Gate Compression for Stall-Free Sparse-Model Access.

[BibT_eX]

[DOI]

Younghoon Byun

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

A 5.76 Gb/s 79.7 pJ/b 128×32 Massive Deep-Learning Uplink MIMO Detector in 28nm CMOS Technology.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2024

2023

Block Orthogonal Sparse Superposition Codes for Ultra-Reliable Low-Latency Communications.

[BibT_eX]

[DOI]

IEEE Trans. Commun., December, 2023

A Scalable Precoding Processor for Large-Scale MU-MIMO Systems.

[BibT_eX]

[DOI]

Namyoon Lee

IEEE Trans. Circuits Syst. I Regul. Pap., July, 2023

Simplified Compressor and Encoder Designs for Low-Cost Approximate Radix-4 Booth Multiplier.

[BibT_eX]

[DOI]

Gunho Park

Jaeha Kung

IEEE Trans. Circuits Syst. II Express Briefs, March, 2023

Low-Latency SCL Polar Decoder Architecture Using Overlapped Pruning Operations.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., March, 2023

Cost-Efficient GPIP Processing for Large-Scale Multi-User MIMO Systems.

[BibT_eX]

[DOI]

Namyoon Lee

IEEE Access, 2023

Optimizations of Privacy-Preserving DNN for Low-Latency Inference on Encrypted Data.

[BibT_eX]

[DOI]

Hyunhoon Lee

IEEE Access, 2023

Sparsity-Aware Memory Interface Architecture using Stacked XORNet Compression for Accelerating Pruned-DNN Models.

[BibT_eX]

[DOI]

Proceedings of the Sixth Conference on Machine Learning and Systems, 2023

Low-Complexity Phase Shift Design for IRS-Aided SU-MIMO Wireless Systems.

[BibT_eX]

[DOI]

Jiwon Kim

Proceedings of the 20th International SoC Design Conference, 2023

Energy-Efficient RISC-V-Based Vector Processor for Cache-Aware Structurally-Pruned Transformers.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023

Analysis of Deep Learning-based MIMO Detectors.

[BibT_eX]

[DOI]

Proceedings of the 14th International Conference on Information and Communication Technology Convergence, 2023

An Automated Synthesis Framework for Fast Evaluation of Maximum Operating Frequency.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Electronics, Information, and Communication, 2023

2022

Low-Complexity Beamforming Optimization for IRS-Aided MU-MIMO Wireless Systems.

[BibT_eX]

[DOI]

IEEE Trans. Veh. Technol., 2022

Area- and Energy-Efficient LDPC Decoder Using Mixed-Resolution Check-Node Processing.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2022

CHAMP: Channel Merging Process for Cost-Efficient Highly-Pruned CNN Acceleration.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Low-Complexity and Low-Latency SVC Decoding Architecture Using Modified MAP-SP Algorithm.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Convolutional Neural Networks With Discrete Cosine Transform Features.

[BibT_eX]

[DOI]

Sanghyeon Ju

Sunggu Lee

IEEE Trans. Computers, 2022

High-Throughput Non-Binary LDPC Decoder Architecture Using Parallel EMS Algorithm.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2022

Simplified Ordered Statistic Decoding for Short-Length Linear Block Codes.

[BibT_eX]

[DOI]

IEEE Commun. Lett., 2022

A 1.1μs 1.56Gb/s/mm2 Cost-Efficient Large-List SCL Polar Decoder Using Fully-Reusable LLR Buffers in 28nm CMOS Technology.

[BibT_eX]

[DOI]

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

Hardware Analysis of Channel Estimation Method for IRS-Aided MIMO Wireless Systems.

[BibT_eX]

[DOI]

Jiwon Kim

Proceedings of the 19th International SoC Design Conference, 2022

Design and Evaluation Frameworks for Advanced RISC-based Ternary Processor.

[BibT_eX]

[DOI]

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

A 2.86Gb/s Fully-Flexible MU-MIMO Processor for Jointly Optimizing User Selection, Power Allocation, and Precoding in 28nm CMOS Technology.

[BibT_eX]

[DOI]

Namyoon Lee

Proceedings of the IEEE Custom Integrated Circuits Conference, 2022

A Study On Reliable High-Speed HBC Enhanced by ECC for Wearable Neural Interfaces.

[BibT_eX]

[DOI]

Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022

2021

Ultralow-Latency Successive Cancellation Polar Decoding Architecture Using Tree-Level Parallelism.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2021

Design and Analysis of Approximate Compressors for Balanced Error Accumulation in MAC Operator.

[BibT_eX]

[DOI]

Gunho Park

Jaeha Kung

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Layerwise Buffer Voltage Scaling for Energy-Efficient Convolutional Neural Network.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Low-Cost Network Scheduling of 3D-CNN Processing for Embedded Action Recognition.

[BibT_eX]

[DOI]

IEEE Access, 2021

Low-Complexity Voice Activity Detection Algorithm for Edge-Level Device.

[BibT_eX]

[DOI]

Jin Hyun

Proceedings of the 18th International SoC Design Conference, 2021

Rapid Design Space Exploration of Near-Optimal Memory-Reduced DCNN Architecture Using Multiple Model Compression Techniques.

[BibT_eX]

[DOI]

Younghoon Byun

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Low-Latency Polar Decoder Using Overlapped SCL Processing.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 2021

Approach to Improve the Performance Using Bit-level Sparsity in Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Energy-Efficient Intelligent EPTS Device using Novel DCNN-Based Dynamic Sensor Activation.

[BibT_eX]

[DOI]

Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021

Utilizing Energy-Quality Trade-Off for Low-Cost ML-Based Compressive Sensing Reconstruction.

[BibT_eX]

[DOI]

Hyunsung Kim

Proceedings of the 55th Asilomar Conference on Signals, Systems, and Computers, 2021

2020

Low-Latency Unfolded-KES Architecture for Emerging Storage Class Memories.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2020

Energy-Efficient Wearable EPTS Device Using On-Device DCNN Processing for Football Activity Classification.

[BibT_eX]

[DOI]

Sensors, 2020

Low-Complexity DNN-Based End-to-End Automatic Speech Recognition using Low-Rank Approximation.

[BibT_eX]

[DOI]

Jongmin Park

Proceedings of the International SoC Design Conference, 2020

High-Quality HTTP Live Streaming System for Limited Communication Bandwidth.

[BibT_eX]

[DOI]

Jung Gyu Min

Proceedings of the International SoC Design Conference, 2020

Ultra-Low-Latency LDPC Decoding Architecture using Reweighted Offset Min-Sum Algorithm.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Energy-Efficient Precoding Architecture for Multi-User MIMO Systems.

[BibT_eX]

[DOI]

Proceedings of the 54th Asilomar Conference on Signals, Systems, and Computers, 2020

Hierarchical Approximate Memory for Deep Neural Network Applications.

[BibT_eX]

[DOI]

Proceedings of the 54th Asilomar Conference on Signals, Systems, and Computers, 2020

2019

Rapid Balise Telegram Decoder With Modified LFSR Architecture for Train Protection Systems.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2019

Energy-Efficient Symmetric BC-BCH Decoder Architecture for Mobile Storages.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Memory-Reduced Network Stacking for Edge-Level CNN Architecture With Structured Weight Pruning.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2019

Massive MIMO Systems With Low-Resolution ADCs: Baseband Energy Consumption vs. Symbol Detection Performance.

[BibT_eX]

[DOI]

IEEE Access, 2019

Selective Deep Convolutional Neural Network for Low Cost Distorted Image Classification.

[BibT_eX]

[DOI]

IEEE Access, 2019

Design of a Low-Power BLE5-Based Wearable Device for Tracking Movements of Football Players.

[BibT_eX]

[DOI]

Proceedings of the 2019 International SoC Design Conference, 2019

WMixNet: An Energy-Scalable and Computationally Lightweight Deep Learning Accelerator.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

Similarity-Based LSTM Architecture for Energy-Efficient Edge-Level Speech Recognition.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

Ultra-Low-Latency Parallel SC Polar Decoding Architecture for 5G Wireless Communications.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Low-Complexity Dynamic Channel Scaling of Noise-Resilient CNN for Intelligent Edge Devices.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

FPGA-Based Sparsity-Aware CNN Accelerator for Noise-Resilient Edge-Level Image Recognition.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019

Multi-level Weight Indexing Scheme for Memory-Reduced Convolutional Neural Network.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems, 2019

2018

Area-Optimized Fully-Flexible BCH Decoder for Multiple GF Dimensions.

[BibT_eX]

[DOI]

Byeonggil Park

Jongsun Park

IEEE Access, 2018

Fixed-Point Quantization of 3D Convolutional Neural Networks for Energy-Efficient Action Recognition.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2018

Multi-Mode LSTM Network for Energy-Efficient Speech Recognition.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2018

A 2.4pJ/bit, 6.37Gb/s SPC-enhanced BC-BCH decoder in 65nm CMOS for NAND flash storage systems.

[BibT_eX]

[DOI]

Jaehwan Jung

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017

Novel Folded-KES Architecture for High-Speed and Area-Efficient BCH Decoders.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2017

High-performance two-step lagrange interpolation technique for 4K UHD applications.

[BibT_eX]

[DOI]

Yunho Park

Youngmin Kim

Proceedings of the International SoC Design Conference, 2017

An energy-optimized (37840, 34320) symmetric BC-BCH decoder for healthy mobile storages.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

2016

Low-Power Parallel Chien Search Architecture Using a Two-Step Approach.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2016

Memory-Reduced Turbo Decoding Architecture Using NII Metric Compression.

[BibT_eX]

[DOI]

Meng Li

Liesbet Van der Perre

IEEE Trans. Circuits Syst. II Express Briefs, 2016

Energy-Scalable 4KB LDPC Decoding Architecture for NAND-Flash-Based Storage Systems.

[BibT_eX]

[DOI]

Jaehwan Jung

IEICE Trans. Electron., 2016

Area-efficient and high-speed binary divider architecture for bit-serial interfaces.

[BibT_eX]

[DOI]

Yunho Park

Jonghyuk Kwon

Proceedings of the International SoC Design Conference, 2016

Sharpness-aware real-time haze removal for advanced driver assistance systems.

[BibT_eX]

[DOI]

Joonggeun Ahn

Jihoon Kim

Proceedings of the International SoC Design Conference, 2016

FPGA-based real-time lane detection for advanced driver assistance systems.

[BibT_eX]

[DOI]

Seokha Hwang

Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

2015

Low-Complexity Tree Architecture for Finding the First Two Minima.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2015

Efficient Parallel Architecture for Linear Feedback Shift Registers.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2015

2014

High-Throughput and Low-Complexity BCH Decoding Architecture for Solid-State Drives.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

7.3 Gb/s universal BCH encoder and decoder for SSD controllers.

[BibT_eX]

[DOI]

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013

A 2.74-pJ/bit, 17.7-Gb/s Iterative Concatenated-BCH Decoder in 65-nm CMOS for NAND Flash Memory.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2013

A 3Gb/s 2.08mm2 100b error-correcting BCH decoder in 0.13µm CMOS process.

[BibT_eX]

[DOI]

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012

6.4Gb/s multi-threaded BCH encoder and decoder for multi-channel SSD controllers.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

Low-latency area-efficient decoding architecture for shortened reed-solomon codes.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2012

Small-area parallel syndrome calculation for strong BCH decoding.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Conference on Acoustics, 2012

2011

Low-Complexity Parallel Chien Search Structure Using Two-Dimensional Optimization.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2011

Statistical modeling of capacitor mismatch effects for successive approximation register ADCs.

[BibT_eX]

[DOI]

Jinook Song

Proceedings of the International SoC Design Conference, 2011

2010

Design of a Scalable and Programmable Sound Synthesizer.

[BibT_eX]

[DOI]

Tae-Hwan Kim

IEEE Trans. Very Large Scale Integr. Syst., 2010

Capacitor array structure and switching control scheme to reduce capacitor mismatch effects for SAR analog-to-digital converters.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Low-complex BPSK demodulation using absolute comparison.

[BibT_eX]

[DOI]

Goeun Lim

Proceedings of the 17th IEEE International Conference on Electronics, 2010

2009

A Scalable and Programmable Sound Synthesizer.

[BibT_eX]

[DOI]

Tae-Hwan Kim