Byeong Yong Kong

Orcid: 0000-0001-5823-5505

According to our database1, Byeong Yong Kong authored at least 25 papers between 2012 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Low-Latency SCL Polar Decoder Architecture Using Overlapped Pruning Operations.
IEEE Trans. Circuits Syst. I Regul. Pap., March, 2023

An Automated Synthesis Framework for Fast Evaluation of Maximum Operating Frequency.
Proceedings of the International Conference on Electronics, Information, and Communication, 2023

2022
Area- and Energy-Efficient LDPC Decoder Using Mixed-Resolution Check-Node Processing.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

A 97-mW Bitwise-Early-Terminating Multiuser Detector for IDMA Systems.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

A 1.1μs 1.56Gb/s/mm<sup>2</sup> Cost-Efficient Large-List SCL Polar Decoder Using Fully-Reusable LLR Buffers in 28nm CMOS Technology.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2021
Real-Time SSDLite Object Detection on FPGA.
IEEE Trans. Very Large Scale Integr. Syst., 2021

Bitwise Early Termination of Multiuser Detection for IDMA Systems.
IEEE Commun. Lett., 2021

Low-Latency Polar Decoder Using Overlapped SCL Processing.
Proceedings of the IEEE International Conference on Acoustics, 2021

2020
A 120-mW 0.16-ms-Latency Connectivity-Scalable Multiuser Detector for Interleave Division Multiple Access.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

A Low-Latency Multi-Touch Detector Based on Concurrent Processing of Redesigned Overlap Split and Connected Component Analysis.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

Retrain-Less Weight Quantization for Multiplier-Less Convolutional Neural Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

Ultra-Low-Latency LDPC Decoding Architecture using Reweighted Offset Min-Sum Algorithm.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Improved Parallel-IDMA Architecture with Low-Complexity Elementary Signal Estimators.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019
Parallel IDMA Architecture Based on Interleaving with Replicated Subpatterns.
Proceedings of the 2019 IEEE International Conference on Communications, 2019

2018
A Memory-Efficient IDMA Architecture Based on On-the-Fly Despreading.
IEEE J. Solid State Circuits, 2018

Efficient Implementation of Multiple Interleavers in IDMA for 5G.
Proceedings of the International SoC Design Conference, 2018

Interference Cancellation Architecture for Pipelined Parallel MIMO Detectors.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

2017
Improved Sorting Architecture for K-Best MIMO Detection.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

2016
Efficient Sorting Architecture for Successive-Cancellation-List Decoding of Polar Codes.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

Low-complexity symbol detection for massive MIMO uplink based on Jacobi method.
Proceedings of the 27th IEEE Annual International Symposium on Personal, 2016

2015
Narrow-range frequency estimation based on comprehensive optimization of DFT and interpolation.
Proceedings of the 2015 IEEE International Conference on Acoustics, 2015

2014
Low-Complexity Low-Latency Architecture for Matching of Data Encoded With Hard Systematic Error-Correcting Codes.
IEEE Trans. Very Large Scale Integr. Syst., 2014

2013
Efficient Tree-Traversal Strategy for Soft-Output MIMO Detection Based on Candidate-Set Reorganization.
IEEE Commun. Lett., 2013

Adaptive Metric Calculation for Improving Detection Capability of MIMO Detectors.
Proceedings of the 77th IEEE Vehicular Technology Conference, 2013

2012
FIR Filter Synthesis Based on Interleaved Processing of Coefficient Generation and Multiplier-Block Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012


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