Jaehwan Jung

According to our database1, Jaehwan Jung authored at least 12 papers between 2013 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2019
Energy-Efficient Symmetric BC-BCH Decoder Architecture for Mobile Storages.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

2018
Interference Cancellation Architecture for Pipelined Parallel MIMO Detectors.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

A 2.4pJ/bit, 6.37Gb/s SPC-enhanced BC-BCH decoder in 65nm CMOS for NAND flash storage systems.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017
Multi-Bit Flipping Decoding of LDPC Codes for NAND Storage Systems.
IEEE Commun. Lett., 2017

An energy-optimized (37840, 34320) symmetric BC-BCH decoder for healthy mobile storages.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

2016
Area-Efficient Approach for Generating Quantized Gaussian Noise.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

Energy-Scalable 4KB LDPC Decoding Architecture for NAND-Flash-Based Storage Systems.
IEICE Trans. Electron., 2016

2015
Low-Complexity Tree Architecture for Finding the First Two Minima.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

Efficient Parallel Architecture for Linear Feedback Shift Registers.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

Unidirectional ring ethernet for low-complexity in-vehicle control network.
Proceedings of the IEEE International Conference on Industrial Technology, 2015

2013
Area-Efficient Multimode Encoding Architecture for Long BCH Codes.
IEEE Trans. Circuits Syst. II Express Briefs, 2013

A 2.74-pJ/bit, 17.7-Gb/s Iterative Concatenated-BCH Decoder in 65-nm CMOS for NAND Flash Memory.
IEEE J. Solid State Circuits, 2013


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