Huimei Cheng

According to our database1, Huimei Cheng authored at least 12 papers between 2016 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2022
Converting Flip-Flop to Clock-Gated 3-Phase Latch-Based Designs Using Graph-Based Retiming.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

2020
SERAD: Soft Error Resilient Asynchronous Design Using a Bundled Data Protocol.
IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020

Saving Power by Converting Flip-Flop to 3-Phase Latch-Based Designs.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
Automatic Retiming of Two-Phase Latch-Based Resilient Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Study on the influence of bus front-end intrusion-free distance to the bus moving characteristics.
Math. Comput. Simul., 2019

Yield modelling and analysis of bundled data and ring-oscillator based designs.
IET Comput. Digit. Tech., 2019

Automatic Conversion from Flip-flop to 3-phase Latch-based Designs.
CoRR, 2019

2018
Area Optimization of Timing Resilient Designs Using Resynthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Challenges in Building an Open-Source Flow from RTL to Bundled-Data Design.
Proceedings of the 24th IEEE International Symposium on Asynchronous Circuits and Systems, 2018

2017
Deadline-Aware Joint Optimization of Sleep Transistor and Supply Voltage for FinFET Based Embedded Systems.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Test Margin and Yield in Bundled Data and Ring-Oscillator Based Designs.
Proceedings of the 23rd IEEE International Symposium on Asynchronous Circuits and Systems, 2017

2016
Area optimization of resilient designs guided by a mixed integer geometric program.
Proceedings of the 53rd Annual Design Automation Conference, 2016


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