Sai Aparna Aketi

Orcid: 0000-0003-3446-0243

According to our database1, Sai Aparna Aketi authored at least 15 papers between 2018 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Towards Two-Stream Foveation-based Active Vision Learning.
CoRR, 2024

Averaging Rate Scheduler for Decentralized Learning on Heterogeneous Data.
CoRR, 2024

Cross-feature Contrastive Loss for Decentralized Deep Learning on Heterogeneous Data.
Proceedings of the IEEE/CVF Winter Conference on Applications of Computer Vision, 2024

2023
Homogenizing Non-IID datasets via In-Distribution Knowledge Distillation for Decentralized Learning.
CoRR, 2023

CoDeC: Communication-Efficient Decentralized Continual Learning.
CoRR, 2023

Global Update Tracking: A Decentralized Learning Algorithm for Heterogeneous Data.
Proceedings of the Advances in Neural Information Processing Systems 36: Annual Conference on Neural Information Processing Systems 2023, 2023

2022
Low precision decentralized distributed training over IID and non-IID data.
Neural Networks, 2022

Neighborhood Gradient Clustering: An Efficient Decentralized Learning Method for Non-IID Data Distributions.
CoRR, 2022

2021
Low Precision Decentralized Distributed Training with Heterogeneous Data.
CoRR, 2021

Sparse-Push: Communication- & Energy-Efficient Decentralized Distributed Learning over Directed & Time-Varying Graphs with non-IID Datasets.
CoRR, 2021

2020
SERAD: Soft Error Resilient Asynchronous Design Using a Bundled Data Protocol.
IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020

Relevant-features based Auxiliary Cells for Energy Efficient Detection of Natural Errors.
CoRR, 2020

Gradual Channel Pruning While Training Using Feature Relevance Scores for Convolutional Neural Networks.
IEEE Access, 2020

2019
Towards Scalable, Efficient and Accurate Deep Spiking Neural Networks with Backward Residual Connections, Stochastic Softmax and Hybridization.
CoRR, 2019

2018
Single-Error Hardened and Multiple-Error Tolerant Guarded Dual Modular Redundancy Technique.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018


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