Hyung-Rok Lee

According to our database, Hyung-Rok Lee authored at least 4 papers between 1998 and 2011.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2011

250 Mbps-5 Gbps Wide-Range CDR With Digital Vernier Phase Shifting and Dual-Mode Control in 0.13 μ m CMOS.

Sang-Yoon Lee, Hyung-Rok Lee, Young-Ho Kwak, Woo-Seok Choi, Byoung-Joo Yoo, Daeyun Shim, Chulwoo Kim, Deog-Kyoon Jeong

IEEE J. Solid State Circuits, 2011

2006

A PVT-Tolerant Low-1/f Noise Dual-Loop Hybrid PLL in 0.18µm.

Hyung-Rok Lee, Ook Kim, Keewook Jung, John Shin, Deog-Kyoon Jeong

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2005

A 1.2-V-only 900-mW 10 gb ethernet transceiver and XAUI interface with robust VCO tuning technique.

Hyung-Rok Lee, Moon-Sang Hwang, Bong-Joon Lee, Young-Deok Kim, Dohwan Oh, Jaeha Kim, Sang-Hyun Lee, Deog-Kyoon Jeong, Wonchan Kim

IEEE J. Solid State Circuits, 2005

1998

Design and Implementation of OTCA MAC Protocol for High-Speed Point-to-Point Ring Network.

Yeshik Shin, Jin-su Ahn, Hyung-Rok Lee, Deog-Kyoon Jeong

Proceedings of the Proceedings 23rd Conference on Local Computer Networks, 1998