Wonchan Kim

According to our database, Wonchan Kim authored at least 31 papers between 1994 and 2007.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2007

A 0.25-µm CMOS 1.9-GHz PHS RF Transceiver With a 150-kHz Low-IF Architecture.

Hoesam Jeong, Byoung-Joo Yoo, Cheol Kyu Han, Sang-Yoon Lee, Kang-Yoon Lee, Suhwan Kim, Deog-Kyoon Jeong, Wonchan Kim

IEEE J. Solid State Circuits, 2007

A 2.8Gb/s All-Digital CDR with a 10b Monotonic DCO.

Do-Hwan Oh, Deok-Soo Kim, Suhwan Kim, Deog-Kyoon Jeong, Wonchan Kim

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2006

A partially switched-opamp technique for high-speed low-power pipelined analog-to-digital converters.

Hwi-Cheol Kim, Deog-Kyoon Jeong, Wonchan Kim

IEEE Trans. Circuits Syst. I Regul. Pap., 2006

A 20-GHz phase-locked loop for 40-gb/s serializing transmitter in 0.13-μm CMOS.

Jaeha Kim, Jeong-Kyoum Kim, Bong-Joon Lee, Namhoon Kim, Deog-Kyoon Jeong, Wonchan Kim

IEEE J. Solid State Circuits, 2006

2005

A 1.2-V-only 900-mW 10 gb ethernet transceiver and XAUI interface with robust VCO tuning technique.

Hyung-Rok Lee, Moon-Sang Hwang, Bong-Joon Lee, Young-Deok Kim, Dohwan Oh, Jaeha Kim, Sang-Hyun Lee, Deog-Kyoon Jeong, Wonchan Kim

IEEE J. Solid State Circuits, 2005

Comparison frequency doubling and charge pump matching techniques for dual-band ΔΣ fractional-N frequency synthesizer.

Hyungki Huh, Yido Koo, Kang-Yoon Lee, Yeonkyeong Ok, Sungho Lee, Daehyun Kwon, Jeongwoo Lee, Joonbae Park, Kyeongho Lee, Deog-Kyoon Jeong, Wonchan Kim

IEEE J. Solid State Circuits, 2005

2003

Full-CMOS 2-GHz WCDMA direct conversion transmitter and receiver.

Kang-Yoon Lee, Seung-Wook Lee, Yido Koo, Hyoung-Ki Huh, Hee-Young Nam, Jeong-Woo Lee, Joonbae Park, Kyeongho Lee, Deog-Kyoon Jeong, Wonchan Kim

IEEE J. Solid State Circuits, 2003

A dual-mode direct-conversion CMOS transceiver for Bluetooth and 802.11b.

Yeon-Jae Jung, Hoesam Jeong, Eunseok Song, Jungho Lee, Seung-Wook Lee, Donghyeon Seo, Inho Song, Sanghun Jung, Joonbae Park, Deog-Kyoon Jeong, Wonchan Kim

Proceedings of the ESSCIRC 2003, 2003

2002

A digital-to-analog converter based on differential-quad switching.

Sungkyung Park, Gyudong Kim, Sin-Chong Park, Wonchan Kim

IEEE J. Solid State Circuits, 2002

A 5-Gb/s 0.25-μm CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit.

Sang-Hyun Lee, Moon-Sang Hwang, Youngdon Choi, Sungjoon Kim, Yongsam Moon, Bong-Joon Lee, Deog-Kyoon Jeong, Wonchan Kim, Young-June Park, Gijung Ahn

IEEE J. Solid State Circuits, 2002

A fully integrated CMOS frequency synthesizer with charge-averaging charge pump and dual-path loop filter for PCS- and cellular-CDMA wireless systems.

Yido Koo, Hyungki Huh, Yongsik Cho, Jeongwoo Lee, Joonbae Park, Kyeongho Lee, Deog-Kyoon Jeong, Wonchan Kim

IEEE J. Solid State Circuits, 2002

2001

Design of a 1.8 GHz low-noise amplifier for RF front-end in a 0.8 μm CMOS technology.

Sungkyung Park, Wonchan Kim

IEEE Trans. Consumer Electron., 2001

Split-level precharge differential logic: a new type of high-speed charge-recycling differential logic.

Jungho Lee, Joonbae Park, Byungjoon Song, Wonchan Kim

IEEE J. Solid State Circuits, 2001

A single-chip 2.4-GHz direct-conversion CMOS receiver for wireless local loop using multiphase reduced frequency conversion technique.

Kyeongho Lee, Joonbae Park, Jeong-Woo Lee, Seung-Wook Lee, Hyung Ki Huh, Deog-Kyoon Jeong, Wonchan Kim

IEEE J. Solid State Circuits, 2001

A dual-loop delay-locked loop using multiple voltage-controlled delay lines.

Yeon-Jae Jung, Seung-Wook Lee, Daeyun Shim, Wonchan Kim, Changhyun Kim, Soo-In Cho

IEEE J. Solid State Circuits, 2001

1999

An image resolution enhancing technique using adaptive sub-pixel interpolation for digital still camera system.

Yido Koo, Wonchan Kim

IEEE Trans. Consumer Electron., 1999

A process and environment tolerant 3V, 2 GHz VCO with 0.8 μm CMOS technology.

Keewook Jung, Changsik Yoo, Hyun-Kyu Yu, Wonchui Song, Wonchan Kim

IEEE Trans. Consumer Electron., 1999

An analog synchronous mirror delay for high-speed DRAM application.

Daeyun Shim, Dong-Yun Lee, Sanghun Jung, Chang-Hyun Kim, Wonchan Kim

IEEE J. Solid State Circuits, 1999

Current sensing differential logic: a CMOS logic for high reliability and flexibility.

Joonbae Park, Jeongho Lee, Wonchan Kim

IEEE J. Solid State Circuits, 1999

A 600-dpi capacitive fingerprint sensor chip and image-synthesis technique.

Jeong-Woo Lee, Dong-Jin Min, Jiyoun Kim, Wonchan Kim

IEEE J. Solid State Circuits, 1999

A Semi-Digital Delay Locked Loop for Clock Skew Minimization.

Joonbae Park, Yido Koo, Wonchan Kim

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

A load-adaptive, low switching-noise data output buffer.

Seung-Wook Lee, Daeyun Shim, Yeon-Jae Jung, Dong-Yun Lee, Chang-Hyun Kim, Wonchan Kim

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

1998

A ±1.5-V, 4-MHz CMOS continuous-time filter with a single-integrator based tuning.

Changsik Yoo, Seung-Wook Lee, Wonchan Kim

IEEE J. Solid State Circuits, 1998

A ±1.5V 4MHz Low-Pass Gm-C Filter in CMOS.

Changsik Yoo, Wonchan Kim

Proceedings of the ASP-DAC '98, 1998

1996

A low-voltage, low-power CMOS delay element.

Gyudong Kim, Min-Kyu Kim, Byoung-Soo Chang, Wonchan Kim

IEEE J. Solid State Circuits, 1996

A 1.2 GHz CMOS dual-modulus prescaler using new dynamic D-type flip-flops.

Byungsoo Chang, Joonbae Park, Wonchan Kim

IEEE J. Solid State Circuits, 1996

1995

A single chip iΔ-Σ ADC with a built-in variable gain stage and DAC with a charge integrating subconverter for a 5 V 9600-b/s modem.

Daejeong Kim, Jaejin Park, Sungjoon Kim, Deog-Kyoon Jeong, Wonchan Kim

IEEE J. Solid State Circuits, August, 1995

A static power saving TTL-to-CMOS input buffer.

Changsik Yoo, Min-Kyu Kim, Wonchan Kim

IEEE J. Solid State Circuits, May, 1995

1994

Exponential curvature-compensated BiCMOS bandgap references.

In-Yeol Lee, Gyudong Kim, Wonchan Kim

IEEE J. Solid State Circuits, November, 1994

An experimental high-density DRAM cell with a built-in gain stage.

Wonchan Kim, Joongsik Kih, Gyudong Kim, Sanghun Jung, Gijung Ahn

IEEE J. Solid State Circuits, August, 1994

A Multibit Delta-Sigma D/A Converter Using a Charge Integrating Sub-Converter.

Daejong Kim, Jaejin Park, Sungjoon Kim, Deog-Kyoon Jeong, Wonchan Kim

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994