Daeyun Shim

According to our database, Daeyun Shim authored at least 6 papers between 1999 and 2011.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2011

250 Mbps-5 Gbps Wide-Range CDR With Digital Vernier Phase Shifting and Dual-Mode Control in 0.13 μ m CMOS.

Sang-Yoon Lee, Hyung-Rok Lee, Young-Ho Kwak, Woo-Seok Choi, Byoung-Joo Yoo, Daeyun Shim, Chulwoo Kim, Deog-Kyoon Jeong

IEEE J. Solid State Circuits, 2011

2006

A Quad 6Gb/s Multi-rate CMOS Transceiver with TX Rise/Fall-Time Control.

Yongsam Moon, Gijung Ahn, Hoon Choi, Namhoon Kim, Daeyun Shim

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2005

A divide-by-16.5 circuit for 10-gb ethernet transceiver in 0.13-μm CMOS.

Yongsam Moon, Sang-Hyun Lee, Daeyun Shim

IEEE J. Solid State Circuits, 2005

2001

A dual-loop delay-locked loop using multiple voltage-controlled delay lines.

Yeon-Jae Jung, Seung-Wook Lee, Daeyun Shim, Wonchan Kim, Changhyun Kim, Soo-In Cho

IEEE J. Solid State Circuits, 2001

1999

An analog synchronous mirror delay for high-speed DRAM application.

Daeyun Shim, Dong-Yun Lee, Sanghun Jung, Chang-Hyun Kim, Wonchan Kim

IEEE J. Solid State Circuits, 1999

A load-adaptive, low switching-noise data output buffer.

Seung-Wook Lee, Daeyun Shim, Yeon-Jae Jung, Dong-Yun Lee, Chang-Hyun Kim, Wonchan Kim

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999