Hyunsoo Chae

According to our database1, Hyunsoo Chae authored at least 4 papers between 2007 and 2009.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2009
A Low-Jitter Open-Loop All-Digital Clock Generator With Two-Cycle Lock-Time.
IEEE Trans. Very Large Scale Integr. Syst., 2009

A 7 ps Jitter 0.053 mm<sup>2</sup> Fast Lock All-Digital DLL With a Wide Range and High Resolution DCC.
IEEE J. Solid State Circuits, 2009

2007
A 7ps-Jitter 0.053mm2 Fast-Lock ADDLL with Wide-Range and High-Resolution All-Digital DCC.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

A Low-Jitter Open-Loop All-Digital Clock Generator with 2 Cycle Lock-Time.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007


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