Sangdon Jung

According to our database1, Sangdon Jung authored at least 8 papers between 2007 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2023
A Crystal-Less Clock Generator for Low-Power and Low-Cost Sensor Transceivers with 12.9MHz-to-3.3GHz Range, 16.67ppm/°C Inaccuracy from -25°C to 85°C, and 0.25us Settle-Time.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023

2020
NB-IoT and GNSS All-In-One System-On-Chip Integrating RF Transceiver, 23-dBm CMOS Power Amplifier, Power Management Unit, and Clock Management System for Low Cost Solution.
IEEE J. Solid State Circuits, 2020

A 4GHz 0.73psrms-Integrated-Jitter PVT-Insensitive Fractional-N Sub-Sampling Ring PLL with a Jitter-Tracking DLL-Assisted DTC.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

30.2 NB-IoT and GNSS All-in-One System-on-Chip Integrating RF Transceiver, 23dBm CMOS Power Amplifier, Power Management Unit and Clock Management System for Low-Cost Solution.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2019
A Blocker-Tolerant Direct Sampling Receiver for Wireless Multi-Channel Communication in 14nm FinFET CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019

A 9.4MHz-to-2.4GHz Jitter-Power Reconfigurable Fractional-N Ring PLL for Multi-Standard Applications in 7nm FinFET CMOS Technology.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019

2009
A 366kS/s 400uW 0.0013mm<sup>2</sup> frequency-to-digital converter based CMOS temperature sensor utilizing multiphase clock.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2007
A wide-range duty-independent all-digital multiphase clock generator.
Proceedings of the 33rd European Solid-State Circuits Conference, 2007


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