Igor Arsovski

According to our database1, Igor Arsovski authored at least 11 papers between 2005 and 2018.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2018
1.4Gsearch/s 2-Mb/mm<sup>2</sup> TCAM Using Two-Phase-Pre-Charge ML Sensing and Power-Grid Pre-Conditioning to Reduce Ldi/dt Power-Supply Noise by 50%.
IEEE J. Solid State Circuits, 2018

2017
12.4 1.4Gsearch/s 2Mb/mm<sup>2</sup> TCAM using two-phase-precharge ML sensing and power-grid preconditioning to reduce Ldi/dt power-supply noise by 50%.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2013
A 32 nm 0.58-fJ/Bit/Search 1-GHz Ternary Content Addressable Memory Compiler Using Silicon-Aware Early-Predict Late-Correct Sensing With Embedded Deep-Trench Capacitor Noise Mitigation.
IEEE J. Solid State Circuits, 2013

A 64Mb SRAM in 22nm SOI technology featuring fine-granularity power gating and low-energy power-supply-partition techniques for 37% leakage reduction.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

Tail-Bit Tracking circuit with degraded VGS bit-cell mimic array for a 50% search-time and 200mV Vmin improvement in a Ternary Content Addressable Memory.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012
A 64 Mb SRAM in 32 nm High-k Metal-Gate SOI Technology With 0.7 V Operation Enabled by Stability, Write-Ability and Read-Ability Enhancements.
IEEE J. Solid State Circuits, 2012

1Gsearch/sec Ternary Content Addressable Memory compiler with silicon-aware Early-Predict Late-Correct single-ended sensing.
Proceedings of the Symposium on VLSI Circuits, 2012

2011
A 64Mb SRAM in 32nm High-k metal-gate SOI technology with 0.7V operation enabled by stability, write-ability and read-ability enhancements.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2006
Improved Match-Line Test and Repair Methodology Including Power-Supply Noise Testing for Content-Addressable Memories.
Proceedings of the 2006 IEEE International Test Conference, 2006

Self-referenced sense amplifier for across-chip-variation immune sensing in high-performance Content-Addressable Memories.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2005
Low-noise embedded CAM with reduced slew-rate match-lines and asynchronous search-lines.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005


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