Steven Burns

According to our database, Steven Burns authored at least 6 papers between 2003 and 2017.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2017

12.4 1.4Gsearch/s 2Mb/mm² TCAM using two-phase-precharge ML sensing and power-grid preconditioning to reduce Ldi/dt power-supply noise by 50%.

Igor Arsovski, Michael Fragano, Robert M. Houle, Akhilesh Patil, Van Butler, Raymond Kim, Ramon Rodriguez, Tom Maffitt, Joseph J. Oler, John Goss, Christopher Parkinson, Michael A. Ziegerhofer, Steven Burns

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2016

A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access.

Gregory Fredeman, Donald W. Plass, Abraham Mathews, Janakiraman Viraraghavan, Kenneth Reyer, Thomas J. Knips, Thomas Miller, Elizabeth L. Gerhard, Dinesh Kannambadi, Chris Paone, Dongho Lee, Daniel Rainey, Michael A. Sperling, Michael Whalen, Steven Burns, Rajesh Reddy Tummuru, Herbert Ho, Alberto Cestero, Norbert Arnold, Babar A. Khan, Toshiaki Kirihata, Subramanian S. Iyer

IEEE J. Solid State Circuits, 2016

2015

17.4 A 14nm 1.1Mb embedded DRAM macro with 1ns access.

Gregory Fredeman, Donald W. Plass, Abraham Mathews, Kenneth Reyer, Thomas J. Knips, Thomas Miller, Elizabeth L. Gerhard, Dinesh Kannambadi, Chris Paone, Dongho Lee, Daniel Rainey, Michael A. Sperling, Michael Whalen, Steven Burns

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2012

Isolated Preset Architecture for a 32nm SOI embedded DRAM macro.

John Barth, Don Plass, Adis Vehabovic, Rajiv V. Joshi, Rouwaida Kanj, Steven Burns, Todd Weaver

Proceedings of the Symposium on VLSI Circuits, 2012

2005

A 500-MHz multi-banked compilable DRAM macro with direct write and programmable pipelining.

John E. Barth Jr., Darren Anand, Steve Burns, Jeffrey H. Dreibelbis, John A. Fifield, Kevin W. Gorman, Michael R. Nelms, Erik Nelson, Adrian Paparelli, Gary Pomichter, Dale E. Pontius, Stephen Sliva

IEEE J. Solid State Circuits, 2005

2003

A 5.6-ns random cycle 144-Mb DRAM with 1.4 Gb/s/pin and DDR3-SRAM interface.

Harold Pilo, Darren Anand, John Barth, Steve Burns, Phil Corson, Jim Covino, Steve Lamphier

IEEE J. Solid State Circuits, 2003