Ilhan Hatirnaz

According to our database1, Ilhan Hatirnaz authored at least 10 papers between 1999 and 2007.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2007
Early wire characterization for predictable network-on-chip global interconnects.
Proceedings of the Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), 2007

2006
Implementation of Structured ASIC Fabric Using Via-Programmable Differential MCML Cells.
Proceedings of the IFIP VLSI-SoC 2006, 2006

Via-programmable expanded universal logic gate in MCML for structured ASIC applications: circuit design.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2004
Modelling and implementation of twisted differential on-chip interconnects for crosstalk noise reduction.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003
Twisted differential on-chip interconnect architecture for inductive/capacitive crosstalk noise cancellation.
Proceedings of the 2003 International Symposium on System-on-Chip, 2003

Full-custom CMOS realization of a high-performance binary sorting engine with linear area-time complexity.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2000
A Modular and Scalable Architecture for the Realization of High-speed Programmable Rank Order Filters Using Threshold Logic.
VLSI Design, 2000

A compact modular architecture for the realization of high-speed binary sorting engines based on rank ordering.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

A compact modular architecture for high-speed binary sorting.
Proceedings of the IEEE International Conference on Acoustics, 2000

1999
Realization of a programmable rank-order filter architecture using capacitive threshold logic gates.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999


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