Srinivasan Murali

According to our database1, Srinivasan Murali authored at least 59 papers between 2004 and 2018.

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Bibliography

2018
Online Obstructive Sleep Apnea Detection on Medical Wearable Sensors.
IEEE Trans. Biomed. Circuits and Systems, 2018

2016
Methods for reliable estimation of pulse transit time and blood pressure variations using smartphone sensors.
Microprocessors and Microsystems - Embedded Hardware Design, 2016

Low-Power Wearable System for Real-Time Screening of Obstructive Sleep Apnea.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Ultra-Low Power Estimation of Heart Rate Under Physical Activity Using a Wearable Photoplethysmographic System.
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

Touch-based system for beat-to-beat impedance cardiogram acquisition and hemodynamic parameters estimation.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
Design of ultra-low-power smart wearable systems.
Proceedings of the 16th Latin-American Test Symposium, 2015

Energy-aware embedded classifier design for real-time emotion analysis.
Proceedings of the 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2015

Estimation of Blood Pressure and Pulse Transit Time Using Your Smartphone.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

Real-Time Probabilistic Heart-Beat Classification and Correction for Embedded Systems.
Proceedings of the Computing in Cardiology, 2015

A Wearable Device for Physical and Emotional Health Monitoring.
Proceedings of the Computing in Cardiology, 2015

2014
Ultra-Low Power Design of Wearable Cardiac Monitoring Systems.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013
Designing best effort networks-on-chip to meet hard latency constraints.
ACM Trans. Embedded Comput. Syst., 2013

Computing Accurate Performance Bounds for Best Effort Networks-on-Chip.
IEEE Trans. Computers, 2013

2012
A Buffer-Sizing Algorithm for Network-on-Chips with Multiple Voltage-Frequency Islands.
J. Electrical and Computer Engineering, 2012

2011
A DRAM Centric NoC Architecture and Topology Design Approach.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

A Simulation Based Buffer Sizing Algorithm for Network on Chips.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

A Method for Integrating Network-on-Chip Topologies with 3D ICs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

Design and Analysis of NoCs for Low-Power 2D and 3D SoCs.
Proceedings of the Low Power Networks-on-Chip., 2011

2010
Comparative Analysis of NoCs for Two-Dimensional Versus Three-Dimensional SoCs Supporting Multiple Voltage and Frequency Islands.
IEEE Trans. on Circuits and Systems, 2010

SunFloor 3D: A Tool for Networks on Chip Topology Synthesis for 3-D Systems on Chips.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2010

A method to remove deadlocks in Networks-on-Chips with Wormhole flow control.
Proceedings of the Design, Automation and Test in Europe, 2010

Networks on Chips: from research to products.
Proceedings of the 47th Design Automation Conference, 2010

Design of networks on chips for 3D ICs.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
Designing Reliable and Efficient Networks on Chips
Lecture Notes in Electrical Engineering 34, Springer, ISBN: 978-1-4020-9756-0, 2009

Processor Speed Control With Thermal Constraints.
IEEE Trans. on Circuits and Systems, 2009

A floorplan-aware interactive tool flow for NoC design and synthesis.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

A method for calculating hard QoS guarantees for Networks-on-Chip.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

SunFloor 3D: A tool for Networks On Chip topology synthesis for 3D systems on chips.
Proceedings of the Design, Automation and Test in Europe, 2009

NoC topology synthesis for supporting shutdown of voltage islands in SoCs.
Proceedings of the 46th Design Automation Conference, 2009

Minimization of the reconfiguration latency for the mapping of applications on FPGA-based systems.
Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009

Synthesis of networks on chips for 3D systems on chips.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
Network-on-Chip design and synthesis outlook.
Integration, 2008

Temperature Control of High-Performance Multi-core Platforms Using Convex Optimization.
Proceedings of the Design, Automation and Test in Europe, 2008

2007
A Method for Routing Packets Across Multiple Paths in NoCs with In-Order Delivery and Fault-Tolerance Gaurantees.
VLSI Design, 2007

Synthesis of Predictable Networks-on-Chip-Based Interconnect Architectures for Chip Multiprocessors.
IEEE Trans. VLSI Syst., 2007

Timing-Error-Tolerant Network-on-Chip Design Methodology.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

An Application-Specific Design Methodology for On-Chip Crossbar Generation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

Bringing NoCs to 65 nm.
IEEE Micro, 2007

An Application-Specific Design Methodology for STbus Crossbar Generation
CoRR, 2007

Early wire characterization for predictable network-on-chip global interconnects.
Proceedings of the Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), 2007

NoC Design and Implementation in 65nm Technology.
Proceedings of the First International Symposium on Networks-on-Chips, 2007

Temperature-aware processor frequency assignment for MPSoCs using convex optimization.
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007

2006
Designing Routing and Message-Dependent Deadlock Free Networks on Chips.
Proceedings of the VLSI-SoC: Research Trends in VLSI and Systems on Chip, 2006

Designing Message-Dependent Deadlock Free Networks on Chips for Application-Specific Systems on Chips.
Proceedings of the IFIP VLSI-SoC 2006, 2006

Routing Aware Switch Hardware Customization for Networks on Chips.
Proceedings of the 1st International ICST Conference on Nano-Networks, 2006

Reliability Support for On-Chip Memories Using Networks-on-Chip.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

Designing application-specific networks on chips with floorplan information.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

A methodology for mapping multiple use-cases onto networks on chips.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

A multi-path routing strategy with guaranteed in-order packet delivery and fault-tolerance for networks on chip.
Proceedings of the 43rd Design Automation Conference, 2006

A buffer-sizing algorithm for networks on chip using TDMA and credit-based end-to-end flow control.
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

Mapping and configuration methods for multi-use-case networks on chips.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005
NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip.
IEEE Trans. Parallel Distrib. Syst., 2005

Analysis of Error Recovery Schemes for Networks on Chips.
IEEE Design & Test of Computers, 2005

An Application-Specific Design Methodology for STbus Crossbar Generation.
Proceedings of the 2005 Design, 2005

Performance driven reliable link design for networks on chips.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Mapping and physical planning of networks-on-chip architectures with quality-of-service guarantees.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Bandwidth-Constrained Mapping of Cores onto NoC Architectures.
Proceedings of the 2004 Design, 2004

×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip.
Proceedings of the 2004 Design, 2004

SUNMAP: a tool for automatic topology selection and generation for NoCs.
Proceedings of the 41th Design Automation Conference, 2004


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