Frank K. Gürkaynak

According to our database1, Frank K. Gürkaynak authored at least 59 papers between 1999 and 2019.

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Bibliography

2019
A Scalable Near-Memory Architecture for Training Deep Neural Networks on Large In-Memory Datasets.
IEEE Trans. Computers, 2019

2018
An 826 MOPS, 210uW/MHz Unum ALU in 65 nm.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

High speed ASIC implementations of leakage-resilient cryptography.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
Near-Threshold RISC-V Core With DSP Extensions for Scalable IoT Endpoint Devices.
IEEE Trans. VLSI Syst., 2017

An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics.
IEEE Trans. on Circuits and Systems, 2017

Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster.
IEEE Micro, 2017

An Extended Shared Logarithmic Unit for Nonlinear Function Kernel Acceleration in a 65-nm CMOS Multicore Cluster.
J. Solid-State Circuits, 2017

Leakage Bounds for Gaussian Side Channels.
IACR Cryptology ePrint Archive, 2017

An 826 MOPS, 210 uW/MHz Unum ALU in 65 nm.
CoRR, 2017

Multi-core data analytics SoC with a flexible 1.76 Gbit/s AES-XTS cryptographic accelerator in 65 nm CMOS.
Proceedings of the Fourth Workshop on Cryptography and Security in Computing Systems, 2017

2016
Hybrid ASIC/FPGA System for Fully Automatic Stereo-to-Multiview Conversion Using IDW.
IEEE Trans. Circuits Syst. Video Techn., 2016

4.6 A 65nm CMOS 6.4-to-29.2pJ/FLOP@0.8V shared logarithmic floating point unit for acceleration of nonlinear function kernels in a tightly coupled processor cluster.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

Approximate 32-bit floating-point unit design with 53% power-area product reduction.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

High-efficiency logarithmic number unit design based on an improved cotransformation scheme.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing.
Proceedings of the 2016 IEEE Symposium in Low-Power and High-Speed Chips, 2016

Accuracy and Performance Trade-Offs of Logarithmic Number Units in Multi-Core Clusters.
Proceedings of the 23nd IEEE Symposium on Computer Arithmetic, 2016

2015
Automatic multiview synthesis - Prototype demo.
Proceedings of the 2015 Visual Communications and Image Processing, 2015

Automatic multiview synthesis - Towards a mobile system on a chip.
Proceedings of the 2015 Visual Communications and Image Processing, 2015

DRAM or no-DRAM?: exploring linear solver architectures for image domain warping in 28 nm CMOS.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
Dynamic memory-based physically unclonable function for the generation of unique identifiers and true random numbers.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

An Approximate Computing Technique for Reducing the Complexity of a Direct-Solver for Sparse Linear Systems in Real-Time Video Processing.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013
A real-time 720p feature extraction core based on Semantic Kernels Binarized.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

A Complete Real-Time Feature Extraction and Matching System Based on Semantic Kernels Binarized.
Proceedings of the VLSI-SoC: At the Crossroads of Emerging Trends, 2013

Red team vs. blue team hardware trojan analysis: detection of a hardware trojan on an actual ASIC.
Proceedings of the HASP 2013, 2013

2012
Investigating the Potential of Custom Instruction Set Extensions for SHA-3 Candidates on a 16-bit Microcontroller Architecture.
IACR Cryptology ePrint Archive, 2012

FPGA-Based High-Speed Authenticated Encryption System.
Proceedings of the VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design, 2012

Spatially-Varying Image Warping: Evaluations and VLSI Implementations.
Proceedings of the VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design, 2012

A general-transformation EWA view rendering engine for 1080p video in 130 nm CMOS.
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012

Instruction Set Extensions for Cryptographic Hash Functions on a Microcontroller Architecture.
Proceedings of the 23rd IEEE International Conference on Application-Specific Systems, 2012

2010
Efficient and side-channel-aware implementations of elliptic curve cryptosystems over prime fields.
IET Information Security, 2010

Developing a Hardware Evaluation Method for SHA-3 Candidates.
Proceedings of the Cryptographic Hardware and Embedded Systems, 2010

2009
Field Programmable Compressor Trees: Acceleration of Multi-Input Addition on FPGAs.
TRETS, 2009

Evaluating Resistance of MCML Technology to Power Analysis Attacks Using a Simulation-Based Methodology.
Trans. Computational Science, 2009

A current sensing completion detection method for asynchronous pipelines operating in the sub-threshold regime.
I. J. Circuit Theory and Applications, 2009

Breaking ECC2K-130.
IACR Cryptology ePrint Archive, 2009

The Certicom Challenges ECC2-X.
IACR Cryptology ePrint Archive, 2009

GALS for Bursty Data Transfer based on Clock Coupling.
Electron. Notes Theor. Comput. Sci., 2009

2008
Improving the power-delay product in SCL circuits using source follower output stage.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs.
Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, 2008

Novel Front-End Circuit Architectures for Integrated Bio-Electronic Interfaces.
Proceedings of the Design, Automation and Test in Europe, 2008

A Generic Standard Cell Design Methodology for Differential Circuit Styles.
Proceedings of the Design, Automation and Test in Europe, 2008

Design space exploration for field programmable compressor trees.
Proceedings of the 2008 International Conference on Compilers, 2008

2007
Globally Asynchronous, Locally Synchronous Circuits: Overview and Outlook.
IEEE Design & Test of Computers, 2007

A 90nm CMOS cryptographic core with improved fault-tolerance in presence of massive defect density.
Proceedings of the 2nd Internationa ICST Conference on Nano-Networks, 2007

Design and realization of a fault-tolerant 90nm CMOS cryptographic engine capable of performing under massive defect density.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

2006
GALS system design: side channel attack secure cryptographic accelerators.
PhD thesis, 2006

Design Challenges for a Differential-Power-Analysis Aware GALS-based AES Crypto ASIC.
Electron. Notes Theor. Comput. Sci., 2006

GALS at ETH Zurich: Success or Failure.
Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2006), 2006

2004
Power-Analysis Attack on an ASIC AES implementation.
Proceedings of the International Conference on Information Technology: Coding and Computing (ITCC'04), 2004

A 2 Gb/s balanced AES crypto-chip implementation.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

2003
Variable delay ripple carry adder with carry chain interrupt detection.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Self-Timed Ring for Globally-Asynchronous Locally-Synchronous Systems.
Proceedings of the 9th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2003), 2003

2002
2Gbit/s Hardware Realizations of RIJNDAEL and SERPENT: A Comparative Analysis.
Proceedings of the Cryptographic Hardware and Embedded Systems, 2002

A Functional Test Methodology for Globally-Asynchronous Locally-Synchronous Systems.
Proceedings of the 8th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2002), 2002

2000
A Modular and Scalable Architecture for the Realization of High-speed Programmable Rank Order Filters Using Threshold Logic.
VLSI Design, 2000

A compact modular architecture for the realization of high-speed binary sorting engines based on rank ordering.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Higher radix Kogge-Stone parallel prefix adder architectures.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

A compact modular architecture for high-speed binary sorting.
Proceedings of the IEEE International Conference on Acoustics, 2000

1999
Realization of a programmable rank-order filter architecture using capacitive threshold logic gates.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999


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