Stéphane Badel

According to our database1, Stéphane Badel authored at least 15 papers between 2003 and 2011.

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Bibliography

2011
Power-gated MOS current mode logic (PG-MCML): a power aware DPA-resistant standard cell library.
Proceedings of the 48th Design Automation Conference, 2011

2010
Optimization of the wire grid size for differential routing: Analysis and impact on the power-delay-area tradeoff.
Microelectron. J., 2010

ARMADILLO: A Multi-purpose Cryptographic Primitive Dedicated to Hardware.
Proceedings of the Cryptographic Hardware and Embedded Systems, 2010

2009
Optimization of Wire Grid Size for Differential Routing and Impact on the Power-delay-area Tradeoff.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions.
Proceedings of the Cryptographic Hardware and Embedded Systems, 2009

2008
CMOS realization of two-dimensional mixed analog-digital Hamming distance discriminator circuits for real-time imaging applications.
Microelectron. J., 2008

A Generic Standard Cell Design Methodology for Differential Circuit Styles.
Proceedings of the Design, Automation and Test in Europe, 2008

2007
Predictable system interconnects through accurate early wire characterization.
Proceedings of the 2007 IEEE International SOC Conference, 2007

Early wire characterization for predictable network-on-chip global interconnects.
Proceedings of the Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), 2007

A Simulation-Based Methodology for Evaluating the DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies.
Proceedings of the 2007 International Conference on Embedded Computer Systems: Architectures, 2007

Breaking the Power-Delay Tradeoff: Design of Low-Power High-Speed MOS Current-Mode Logic Circuits Operating with Reduced Supply Voltage.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006
Implementation of Structured ASIC Fabric Using Via-Programmable Differential MCML Cells.
Proceedings of the IFIP VLSI-SoC 2006, 2006

Via-programmable expanded universal logic gate in MCML for structured ASIC applications: circuit design.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2004
Mixed analog-digital image processing circuit based on Hamming artificial neural network architecture.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003
VLSI Realization of a Two-Dimensional Hamming Distance Comparator ANN for Image Processing Applications.
Proceedings of the ESANN 2003, 2003


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