Ilya Ganusov

According to our database, Ilya Ganusov authored at least 14 papers between 2004 and 2021.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2021

Clock Skew Scheduling: Avoiding the Runtime Cost of Mixed-Integer Linear Programming.

Grace Zgheib, Yu Shen Lu, Ilya Ganusov

Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021

2020

Agilex™ Generation of Intel® FPGAs.

Ilya K. Ganusov, Mahesh A. Iyer, Ning Cheng, Alon Meisler

Proceedings of the IEEE Hot Chips 32 Symposium, 2020

Architectural Enhancements in Intel® Agilex™ FPGAs.

Jeffrey Chromczak, Mark Wheeler, Charles Chiasson, Dana How, Martin Langhammer, Tim Vanderhoek, Grace Zgheib, Ilya Ganusov

Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020

2016

A 16-nm Multiprocessing System-on-Chip Field-Programmable Gate Array Platform.

Sagheer Ahmad, Vamsi Boppana, Ilya Ganusov, Vinod Kathail, Vidya Rajagopalan, Ralph Wittig

IEEE Micro, 2016

Automated extra pipeline analysis of applications mapped to Xilinx UltraScale+ FPGAs.

Ilya Ganusov, Henri Fraisse, Aaron Ng, Rafael Trapani Possignolo, Sabya Das

Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

Time-borrowing platform in the Xilinx UltraScale+ family of FPGAs and MPSoCs.

Ilya Ganusov, Benjamin Devlin

Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

2015

UltraScale+ MPSoC and FPGA families.

Vamsi Boppana, Sagheer Ahmad, Ilya Ganusov, Vinod Kathail, Vidya Rajagopalan, Ralph Wittig

Proceedings of the 2015 IEEE Hot Chips 27 Symposium (HCS), 2015

2006

Future execution: A prefetching mechanism that uses multiple cores to speed up single threads.

Ilya Ganusov, Martin Burtscher

ACM Trans. Archit. Code Optim., 2006

Efficient emulation of hardware prefetchers via event-driven helper threading.

Ilya Ganusov, Martin Burtscher

Proceedings of the 15th International Conference on Parallel Architectures and Compilation Techniques (PACT 2006), 2006

2005

The VPC Trace-Compression Algorithms.

Martin Burtscher, Ilya Ganusov, Sandra J. Jackson, Jian Ke, Paruj Ratanaworabhan, Nana B. Sam

IEEE Trans. Computers, 2005

Bridging the Processor-Memory Performance Gapwith 3D IC Technology.

Christianto C. Liu, Ilya Ganusov, Martin Burtscher, Sandip Tiwari

IEEE Des. Test Comput., 2005

Future Execution: A Hardware Prefetching Technique for Chip Multiprocessors.

Ilya Ganusov, Martin Burtscher

Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques (PACT 2005), 2005

On the importance of optimizing the configuration of stream prefetchers.

Ilya Ganusov, Martin Burtscher

Proceedings of the 2005 workshop on Memory System Performance, 2005

2004

Automatic Synthesis of High-Speed Processor Simulators.

Martin Burtscher, Ilya Ganusov

Proceedings of the 37th Annual International Symposium on Microarchitecture (MICRO-37 2004), 2004