Rafael Trapani Possignolo

Orcid: 0000-0002-5777-474X

According to our database1, Rafael Trapani Possignolo authored at least 17 papers between 2009 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2020
LiveHD: A Productive Live Hardware Development Flow.
IEEE Micro, 2020

LiveSim: A Fast Hot Reload Simulator for HDLs.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2020

2019
EMI Architectural Model and Core Hopping.
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

SMatch: Structural Matching for Fast Resynthesis in FPGAs.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
Improving the Productivity of Hardware Design.
PhD thesis, 2018

GPU NTC Process Variation Compensation With Voltage Stacking.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Automated Pipeline Transformations with Fluid Pipelines.
Proceedings of the Advanced Logic Synthesis, 2018

2017
Liam: an actor based programming model for HDLs.
Proceedings of the 15th ACM-IEEE International Conference on Formal Methods and Models for System Design, 2017

Level shifter design for voltage stacking.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016
Managing Mismatches in Voltage Stacking with CoreUnfolding.
ACM Trans. Archit. Code Optim., 2016

SRAM voltage stacking.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Fluid Pipelines: Elastic circuitry meets Out-of-Order execution.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

LiveSynth: Towards an interactive synthesis flow.
Proceedings of the 2016 IEEE Hot Chips 28 Symposium (HCS), 2016

Automated extra pipeline analysis of applications mapped to Xilinx UltraScale+ FPGAs.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

2015
Quantum-assisted QD-CFS signatures.
J. Comput. Syst. Sci., 2015

2012
A Quantum-classical Hybrid Architecture for Security Algorithms Acceleration.
Proceedings of the 11th IEEE International Conference on Trust, 2012

2009
Optimized joint NARX ANN - embedded processor design methodology.
Proceedings of the 16th IEEE International Conference on Electronics, 2009


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