Henri Fraisse

Orcid: 0000-0003-1839-0089

According to our database1, Henri Fraisse authored at least 9 papers between 1993 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of five.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
Entropy Maximization in Sparse Matrix by Vector Multiplication (max<sub>E</sub>SpMV).
CoRR, 2023

2020
The Real Effects of Bank Capital Requirements.
Manag. Sci., 2020

A Domain-Specific Architecture for Accelerating Sparse Matrix Vector Multiplication on FPGAs.
Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020

2018
SAT Based Place-And-Route for High-Speed Designs on 2.5D FPGAs.
Proceedings of the International Conference on Field-Programmable Technology, 2018

A SAT-based Timing Driven Place and Route Flow for Critical Soft IP.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

2016
Automated extra pipeline analysis of applications mapped to Xilinx UltraScale+ FPGAs.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

Boolean Satisfiability-Based Routing and Its Application to Xilinx UltraScale Clock Network.
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

2015
Analyzing the divide between FPGA academic and commercial results.
Proceedings of the 2015 International Conference on Field Programmable Technology, 2015

1993
A New Viewpoint on Two-Level Logic Minimization.
Proceedings of the 30th Design Automation Conference. Dallas, 1993


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