Mahesh A. Iyer

According to our database1, Mahesh A. Iyer authored at least 24 papers between 1992 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.



In proceedings 
PhD thesis 




Symbiosis in Action: Reconfigurable Architectures and EDA.
Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020

High-Definition Routing Congestion Prediction for Large-Scale FPGAs.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

FPGA-Accelerated Spreading for Global Placement.
Proceedings of the 2019 IEEE High Performance Extreme Computing Conference, 2019

FPGA Accelerated FPGA Placement.
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

A shape-driven spreading algorithm using linear programming for global placement.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

CAD Opportunities with Hyper-Pipelining.
Proceedings of the 2017 ACM on International Symposium on Physical Design, 2017

An Effective Timing-Driven Detailed Placement Algorithm for FPGAs.
Proceedings of the 2017 ACM on International Symposium on Physical Design, 2017

LSC: A Large-Scale Consensus-Based Clustering Algorithm for High-Performance FPGAs.
Proceedings of the 54th Annual Design Automation Conference, 2017

Detailed placement for modern FPGAs using 2D dynamic programming.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

On improving optimization effectiveness in interconnect-driven physical synthesis.
Proceedings of the 2009 International Symposium on Physical Design, 2009

A Robust and Scalable Technique for the Constraints Solving Problem in High-Level Verification.
Proceedings of the Fourth International Workshop on Microprocessor Test and Verification, 2003

Race: A Word-Level ATPG-Based Constraints Solver System For Smart Random Simulation.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

FILL and FUNI: algorithms to identify illegal states and sequentially untestable faults.
ACM Trans. Design Autom. Electr. Syst., 2000

High Time For High Level ATPG.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

A Robust Solution to the Timing Convergence Problem in High-Performance Design.
Proceedings of the IEEE International Conference On Computer Design, 1999

Wavefront Technology Mapping.
Proceedings of the 1999 Design, 1999

FIRE: a fault-independent combinational redundancy identification algorithm.
IEEE Trans. Very Large Scale Integr. Syst., 1996

Surprises in Sequential Redundancy Identification.
Proceedings of the 1996 European Design and Test Conference, 1996

Identifying Sequential Redundancies Without Search.
Proceedings of the 33st Conference on Design Automation, 1996

Energy models for delay testing.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1995

Identifying sequentially untestable faults using illegal states.
Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

Low-Cost Redundancy Identification for Combinatorial Circuits.
Proceedings of the Seventh International Conference on VLSI Design, 1994

Sequentially Untestable Faults Identified Without Search ("Simple Implications Beat Exhaustive Search!").
Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

One-Pass Redundancy Identification and Removal.
Proceedings of the Proceedings IEEE International Test Conference 1992, 1992