Ioannis Nousias

According to our database1, Ioannis Nousias authored at least 24 papers between 2005 and 2010.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Links

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Bibliography

2010
A dynamically reconfigurable asynchronous processor.
Proceedings of the IEEE 8th Symposium on Application Specific Processors, 2010

A dynamically reconfigurable asynchronous processor for low power applications.
Proceedings of the 2010 Conference on Design & Architectures for Signal & Image Processing, 2010

2009
Reconfigurable instruction cell architecture: reconfiguration and interconnects.
PhD thesis, 2009

Multicore Architectures With Dynamically Reconfigurable Array Processors for Wireless Broadband Technologies.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

2008
The Reconfigurable Instruction Cell Array.
IEEE Trans. Very Large Scale Integr. Syst., 2008

Efficient Implementation of WiMAX Physical Layer on Multi-core Architectures with Dynamically Reconfigurable Processors.
Scalable Comput. Pract. Exp., 2008

Extensible software emulator for reconfigurable instruction cell based processors.
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

MRPSIM: A TLM based simulation tool for MPSOCS targeting dynamically reconfigurable processors.
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

Multi-core Architectures with Dynamically Reconfigurable Array Processors for the WiMAX Physical Layer.
Proceedings of the IEEE Symposium on Application Specific Processors, 2008

Efficient Implementation of Wireless Applications on Multi-core Platforms Based on Dynamically Reconfigurable Processors.
Proceedings of the Second International Conference on Complex, 2008

2007
Performance analysis of IEEE defined LDPC codes under various decoding algorithms and their implementation on a reconfigurable instruction cell architecture.
Proceedings of the 2007 IEEE International SOC Conference, 2007

Code Compression and Decompression for Instruction Cell Based Reconfigurable Systems.
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

A Multi Objective GA based Physical Placement Algorithm for Heterogeneous Dynamically Reconfigurable Arrays.
Proceedings of the FPL 2007, 2007

H.264/AVC In-Loop De-Blocking Filter Targeting a Dynamically Reconfigurable Instruction Cell Based Architecture.
Proceedings of the FPL 2007, 2007

The Design of Multitasking Based Applications on Reconfigurable Instruction Cell Bsed Architectures.
Proceedings of the FPL 2007, 2007

Mapping Real Time Operating System on Reconfigurable Instruction Cell Based Architectures.
Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, 2007

Code Compressor and Decompressor for Ultra Large Instruction Width Coarse-Grain Reconfigurable Systems.
Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, 2007

A Multi-object GA Based Physical Placement Algorithm for Heterogeneous Dynamicaly Reconfigurable Arrays.
Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 2007

H.264/AVC In-Loop De-Blocking Filter Targeting a Dynamically Reconfigurable Instruction Cell Based Architecture.
Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 2007

2006
H.264 Decoder Implementation on a Dynamically Reconfigurable Instruction Cell Based Architecture.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

System-level scheduling on instruction cell based reconfigurable systems.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Wormhole Routing with Virtual Channels using Adaptive Rate Control for Network-on-Chip (NoC).
Proceedings of the First NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2006), 2006

2005
Automatic synthesis and scheduling of multirate DSP algorithms.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

An AMBA AHB-based reconfigurable SOC architecture using multiplicity of dedicated flyby DMA blocks.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005


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