Mark Muir

According to our database1, Mark Muir authored at least 18 papers between 2007 and 2010.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2010
A dynamically reconfigurable asynchronous processor.
Proceedings of the IEEE 8th Symposium on Application Specific Processors, 2010

A dynamically reconfigurable asynchronous processor for low power applications.
Proceedings of the 2010 Conference on Design & Architectures for Signal & Image Processing, 2010

2009
Re-targetable tools and methodologies for the efficient deployment of high-level source code on coarse-grained dynamically reconfigurable architectures.
PhD thesis, 2009

Multicore Architectures With Dynamically Reconfigurable Array Processors for Wireless Broadband Technologies.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Heterogeneous multi-core architectures with dynamically reconfigurable processors for WiMAX transmitter.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

Heterogeneous multi-core architectures with dynamically reconfigurable processors for wireless communication.
Proceedings of the IEEE 7th Symposium on Application Specific Processors, 2009

2008
The Reconfigurable Instruction Cell Array.
IEEE Trans. Very Large Scale Integr. Syst., 2008

Efficient Implementation of WiMAX Physical Layer on Multi-core Architectures with Dynamically Reconfigurable Processors.
Scalable Comput. Pract. Exp., 2008

Extensible software emulator for reconfigurable instruction cell based processors.
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

MRPSIM: A TLM based simulation tool for MPSOCS targeting dynamically reconfigurable processors.
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

Multi-core Architectures with Dynamically Reconfigurable Array Processors for the WiMAX Physical Layer.
Proceedings of the IEEE Symposium on Application Specific Processors, 2008

Automated Dynamic Throughput-constrained Structural-level Pipelining in Streaming Applications.
Proceedings of the Design, Automation and Test in Europe, 2008

Efficient Implementation of Wireless Applications on Multi-core Platforms Based on Dynamically Reconfigurable Processors.
Proceedings of the Second International Conference on Complex, 2008

2007
A Multi Objective GA based Physical Placement Algorithm for Heterogeneous Dynamically Reconfigurable Arrays.
Proceedings of the FPL 2007, 2007

H.264/AVC In-Loop De-Blocking Filter Targeting a Dynamically Reconfigurable Instruction Cell Based Architecture.
Proceedings of the FPL 2007, 2007

The Design of Multitasking Based Applications on Reconfigurable Instruction Cell Bsed Architectures.
Proceedings of the FPL 2007, 2007

Mapping Real Time Operating System on Reconfigurable Instruction Cell Based Architectures.
Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, 2007

A Multi-object GA Based Physical Placement Algorithm for Heterogeneous Dynamicaly Reconfigurable Arrays.
Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 2007


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