Sami Khawam

According to our database1, Sami Khawam authored at least 33 papers between 2003 and 2010.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2010
A dynamically reconfigurable asynchronous processor.
Proceedings of the IEEE 8th Symposium on Application Specific Processors, 2010

A dynamically reconfigurable asynchronous processor for low power applications.
Proceedings of the 2010 Conference on Design & Architectures for Signal & Image Processing, 2010

2008
The Reconfigurable Instruction Cell Array.
IEEE Trans. Very Large Scale Integr. Syst., 2008

Extensible software emulator for reconfigurable instruction cell based processors.
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

2007
Performance analysis of IEEE defined LDPC codes under various decoding algorithms and their implementation on a reconfigurable instruction cell architecture.
Proceedings of the 2007 IEEE International SOC Conference, 2007

A Multi Objective GA based Physical Placement Algorithm for Heterogeneous Dynamically Reconfigurable Arrays.
Proceedings of the FPL 2007, 2007

H.264/AVC In-Loop De-Blocking Filter Targeting a Dynamically Reconfigurable Instruction Cell Based Architecture.
Proceedings of the FPL 2007, 2007

A Multi-object GA Based Physical Placement Algorithm for Heterogeneous Dynamicaly Reconfigurable Arrays.
Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 2007

H.264/AVC In-Loop De-Blocking Filter Targeting a Dynamically Reconfigurable Instruction Cell Based Architecture.
Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 2007

A Hybrid Engine for the Placement of Domain-Specific Reconfigurable Arrays.
Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 2007

2006
Domain-specific and reconfigurable instruction cells based architectures for low-power SoC.
PhD thesis, 2006

A simple recursive scheme for adjusting the contention window size in IEEE 802.11e wireless ad hoc networks.
Comput. Commun., 2006

H.264 Decoder Implementation on a Dynamically Reconfigurable Instruction Cell Based Architecture.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

System-level scheduling on instruction cell based reconfigurable systems.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Genetic Algorithm based Engine for Domain-Specific Reconfigurable Arrays.
Proceedings of the First NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2006), 2006

Architecture of a Dynamically Reconfigurable NoC for Adaptive Reconfigurable MPSoC.
Proceedings of the First NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2006), 2006

2005
Adaptive approach for QoS support in IEEE 802.11e wireless LAN.
Proceedings of the 2005 IEEE International Conference on Wireless And Mobile Computing, 2005

Architecture and design methodology for synthesizable reconfigurable array targeting wireless system-on-chip applications.
Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005

A Low Power Heterogenous Reconfigurable Architecture For Embedded Generic Finite State Machines.
Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005

Efficient implementation of trace-back unit in a reconfigurable Viterbi decoder fabric.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A Low-Power Reconfigurable Datapath for Advanced Speech Coding Algorithms.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

A domain specific reconfigurable Viterbi fabric for system-on-chip applications.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Automatic synthesis and scheduling of multirate DSP algorithms.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

An AMBA AHB-based reconfigurable SOC architecture using multiplicity of dedicated flyby DMA blocks.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

A high performance synthesisable unsymmetrical reconfigurable fabric for heterogeneous finite state machines.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Video transmission through domain specific reconfigurable architecurtes over short distance wireless medium utilizing Bluetooth IEEE 802.15.1™ standard [architecurtes read architectures].
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

Synthesizable Reconfigurable Array Targeting Distributed Arithmetic for System-on-Chip Applications.
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

Domain specific reconfigurable fabric targeting Viterbi algorithm.
Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, 2004

Switch-box design for synthesizable coarse-grain arrays for system-on-chip applications.
Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, 2004

Unidirectional Switch-Boxes for Synthesizable Reconfigurable Arrays.
Proceedings of the 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 2004

Efficient Implementations of Mobile Video Computations on Domain-Specific Reconfigurable Arrays.
Proceedings of the 2004 Design, 2004

2003
Embedded reconfigurable array targeting motion estimation applications.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Domain-Specific Reconfigurable Array for Distributed Arithmetic.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003


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