Mark Milward

According to our database1, Mark Milward authored at least 17 papers between 2003 and 2013.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2013
Architecture, performance modeling and VLSI implementation methodologies for ASIC vector processors: A case study in telephony workloads.
Microprocess. Microsystems, 2013

2012
Embedded UML design flow to the configurable LE1 MultiCore VLIW processor.
Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012

2008
The Reconfigurable Instruction Cell Array.
IEEE Trans. Very Large Scale Integr. Syst., 2008

Code Compression and Decompression for Coarse-Grain Reconfigurable Architectures.
IEEE Trans. Very Large Scale Integr. Syst., 2008

Extensible software emulator for reconfigurable instruction cell based processors.
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

2007
Performance analysis of IEEE defined LDPC codes under various decoding algorithms and their implementation on a reconfigurable instruction cell architecture.
Proceedings of the 2007 IEEE International SOC Conference, 2007

Code Compression and Decompression for Instruction Cell Based Reconfigurable Systems.
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

A Multi Objective GA based Physical Placement Algorithm for Heterogeneous Dynamically Reconfigurable Arrays.
Proceedings of the FPL 2007, 2007

H.264/AVC In-Loop De-Blocking Filter Targeting a Dynamically Reconfigurable Instruction Cell Based Architecture.
Proceedings of the FPL 2007, 2007

Code Compressor and Decompressor for Ultra Large Instruction Width Coarse-Grain Reconfigurable Systems.
Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, 2007

A Multi-object GA Based Physical Placement Algorithm for Heterogeneous Dynamicaly Reconfigurable Arrays.
Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 2007

H.264/AVC In-Loop De-Blocking Filter Targeting a Dynamically Reconfigurable Instruction Cell Based Architecture.
Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 2007

2006
H.264 Decoder Implementation on a Dynamically Reconfigurable Instruction Cell Based Architecture.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

System-level scheduling on instruction cell based reconfigurable systems.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
Automatic synthesis and scheduling of multirate DSP algorithms.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Design and Implementation of a Lossless Parallel High-Speed Data Compression System.
IEEE Trans. Parallel Distributed Syst., 2004

2003
Routing Strategies for High Speed Parallel Data Compression.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2003


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