Ying Yi

According to our database1, Ying Yi authored at least 31 papers between 2002 and 2018.

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Bibliography

2018
MNDR v2.0: an updated resource of ncRNA-disease associations in mammals.
Nucleic Acids Research, 2018

2017
RAID v2.0: an updated resource of RNA-associated interactions across organisms.
Nucleic Acids Research, 2017

2016
A general method for cupping artifact correction of cone-beam breast computed tomography images.
Int. J. Comput. Assist. Radiol. Surg., 2016

2015
ViRBase: a resource for virus-host ncRNA-associated interactions.
Nucleic Acids Research, 2015

Design and optimization of a 3-coil resonance-based wireless power transfer system for biomedical implants.
I. J. Circuit Theory and Applications, 2015

Electromagnetically powered electrolytic pump and thermo-responsive valve for drug delivery.
Proceedings of the 10th IEEE International Conference on Nano/Micro Engineered and Molecular Systems, 2015

2014
An Improved Electrolytic Pump for Potential Drug Delivery Applications.
Proceedings of the BIODEVICES 2014, 2014

2013
Surface tension-induced high aspect-ratio PDMS micropillars with concave and convex lens tips.
Proceedings of the 8th IEEE International Conference on Nano/Micro Engineered and Molecular Systems, 2013

Low-cost rapid prototyping of flexible plastic paper based microfluidic devices.
Proceedings of the 8th IEEE International Conference on Nano/Micro Engineered and Molecular Systems, 2013

2010
A high-efficiency reconfigurable 2-D Discrete Wavelet Transform engine for JPEG2000 implementation on next generation digital cameras.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

Dual-core reconfigurable demosaicing engine for next generation of portable camera systems.
Proceedings of the 2010 Conference on Design & Architectures for Signal & Image Processing, 2010

2009
Multicore Architectures With Dynamically Reconfigurable Array Processors for Wireless Broadband Technologies.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2009

Heterogeneous multi-core architectures with dynamically reconfigurable processors for WiMAX transmitter.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

Heterogeneous multi-core architectures with dynamically reconfigurable processors for wireless communication.
Proceedings of the IEEE 7th Symposium on Application Specific Processors, 2009

An ILP formulation for task mapping and scheduling on multi-core architectures.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
The Reconfigurable Instruction Cell Array.
IEEE Trans. VLSI Syst., 2008

Efficient Implementation of WiMAX Physical Layer on Multi-core Architectures with Dynamically Reconfigurable Processors.
Scalable Computing: Practice and Experience, 2008

Exploiting loop-level parallelism on multi-core architectures for the wimax physical layer.
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

MRPSIM: A TLM based simulation tool for MPSOCS targeting dynamically reconfigurable processors.
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

Multi-core Architectures with Dynamically Reconfigurable Array Processors for the WiMAX Physical Layer.
Proceedings of the IEEE Symposium on Application Specific Processors, 2008

Efficient Implementation of Wireless Applications on Multi-core Platforms Based on Dynamically Reconfigurable Processors.
Proceedings of the Second International Conference on Complex, 2008

2007
Performance analysis of IEEE defined LDPC codes under various decoding algorithms and their implementation on a reconfigurable instruction cell architecture.
Proceedings of the 2007 IEEE International SOC Conference, 2007

Evaluate E-loyalty of sales website: a Fuzzy mathematics method.
Proceedings of the Integration and Innovation Orient to E-Society, 2007

H.264/AVC In-Loop De-Blocking Filter Targeting a Dynamically Reconfigurable Instruction Cell Based Architecture.
Proceedings of the FPL 2007, 2007

H.264/AVC In-Loop De-Blocking Filter Targeting a Dynamically Reconfigurable Instruction Cell Based Architecture.
Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 2007

2006
Hierarchical synthesis of complex DSP functions using IRIS.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

H.264 Decoder Implementation on a Dynamically Reconfigurable Instruction Cell Based Architecture.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

System-level scheduling on instruction cell based reconfigurable systems.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
High Speed FPGA-Based Implementations of Delayed-LMS Filters.
VLSI Signal Processing, 2005

Automatic synthesis and scheduling of multirate DSP algorithms.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2002
FPGA-based system-level design framework based on the IRIS synthesis tool and System Generator.
Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002


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