Ahmet T. Erdogan
Orcid: 0000-0003-2451-9395
According to our database1,
Ahmet T. Erdogan
authored at least 146 papers
between 1999 and 2022.
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Bibliography
2022
A High Dynamic Range 128 × 120 3-D Stacked CMOS SPAD Image Sensor SoC for Fluorescence Microendoscopy.
IEEE J. Solid State Circuits, 2022
A direct time-of-flight image sensor with in-pixel surface detection and dynamic vision.
CoRR, 2022
2019
A CMOS SPAD Line Sensor With Per-Pixel Histogramming TDC for Time-Resolved Multispectral Imaging.
IEEE J. Solid State Circuits, 2019
A 128×120 5-Wire 1.96mm<sup>2</sup> 40nm/90nm 3D Stacked SPAD Time Resolved Image Sensor SoC for Microendoscopy.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
2013
High-Efficiency Customized Coarse-Grained Dynamically Reconfigurable Architecture for JPEG2000.
IEEE Trans. Very Large Scale Integr. Syst., 2013
Adaptive three-dimensional cellular genetic algorithm for balancing exploration and exploitation processes.
Soft Comput., 2013
J. Parallel Distributed Comput., 2013
Efficient ultra-high-voltage controller-based complementary-metal-oxide-semiconductor switched-capacitor DC-DC converter for radio-frequency micro-electro-mechanical systems switch actuation.
IET Circuits Devices Syst., 2013
Proceedings of the 24th IEEE Annual International Symposium on Personal, 2013
Proceedings of the 2013 NASA/ESA Conference on Adaptive Hardware and Systems, 2013
2012
Novel Dynamic Partial Reconfiguration Implementation of K-Means Clustering on FPGAs: Comparative Results with GPPs and GPUs.
Int. J. Reconfigurable Comput., 2012
2011
Multi-objective evolutionary optimizations of a space-based reconfigurable sensor network under hard constraints.
Soft Comput., 2011
Highly Parameterized K-means Clustering on FPGAs: Comparative Results with GPPs and GPUs.
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011
Proceedings of the 4th IFIP International Conference on New Technologies, 2011
Practical design strategy for two-phase step up DC-DC Fibonacci Switched-Capacitor converter.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011
High performance Intra-task parallelization of Multiple Sequence Alignments on CUDA-compatible GPUs.
Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems, 2011
Enabling FPGAs for future deep space exploration missions: Improving fault-tolerance and computation density with R3TOS.
Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems, 2011
An FPGA-based parameterised and scalable optimal solutions for pairwise biological sequence analysis.
Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems, 2011
FPGA implementation of K-means algorithm for bioinformatics application: An accelerated approach to clustering Microarray data.
Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems, 2011
Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems, 2011
Fault tolerant three-dimensional cellular genetic algorithms with adaptive migration schemes.
Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems, 2011
2010
Interframe Bus Encoding Technique and Architecture for MPEG-4 AVC/H.264 Video Compression.
IEEE Trans. Very Large Scale Integr. Syst., 2010
A high-efficiency reconfigurable 2-D Discrete Wavelet Transform engine for JPEG2000 implementation on next generation digital cameras.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010
Proceedings of the IEEE 8th Symposium on Application Specific Processors, 2010
Proceedings of the IEEE 8th Symposium on Application Specific Processors, 2010
A parallel hybrid merge-select sorting scheme for K-best LSD MIMO decoder on a dynamically reconfigurable processor.
Proceedings of the IEEE 21st International Symposium on Personal, 2010
ASIC Design of an Adaptive Control Unit for Reconfigurable Analog-to-Digital Converters.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010
Dual-core reconfigurable demosaicing engine for next generation of portable camera systems.
Proceedings of the 2010 Conference on Design & Architectures for Signal & Image Processing, 2010
A hybrid dual-core Reconfigurable Processor for EBCOT tier-1 encoder in JPEG2000 on next generation of digital cameras.
Proceedings of the 2010 Conference on Design & Architectures for Signal & Image Processing, 2010
Proceedings of the 2010 Conference on Design & Architectures for Signal & Image Processing, 2010
Proceedings of the 2010 Conference on Design & Architectures for Signal & Image Processing, 2010
Lattice reconfiguration vs. local selection criteria for diversity tuning in cellular GAs.
Proceedings of the IEEE Congress on Evolutionary Computation, 2010
Fault tolerance through automatic cell isolation using three-dimensional cellular genetic algorithms.
Proceedings of the IEEE Congress on Evolutionary Computation, 2010
Adaptive radiation pattern optimization for antenna arrays by phase perturbations using particle swarm optimization.
Proceedings of the 2010 NASA/ESA Conference on Adaptive Hardware and Systems, 2010
Proceedings of the 2010 NASA/ESA Conference on Adaptive Hardware and Systems, 2010
Proceedings of the 2010 NASA/ESA Conference on Adaptive Hardware and Systems, 2010
Balancing exploration and exploitation in an adaptive three-dimensional cellular genetic algorithm via a probabilistic selection operator.
Proceedings of the 2010 NASA/ESA Conference on Adaptive Hardware and Systems, 2010
2009
IEEE Trans. Circuits Syst. Video Technol., 2009
Multicore Architectures With Dynamically Reconfigurable Array Processors for Wireless Broadband Technologies.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
EURASIP J. Embed. Syst., 2009
A novel high-efficiency partial-parallel context modeling architecture for EBCOT in JPEG2000.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009
Heterogeneous multi-core architectures with dynamically reconfigurable processors for WiMAX transmitter.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009
Heterogeneous multi-core architectures with dynamically reconfigurable processors for wireless communication.
Proceedings of the IEEE 7th Symposium on Application Specific Processors, 2009
A SDR platform for mobile Wi-Fi/3G UMTS system on a dynamic reconfigurable architecture.
Proceedings of the 17th European Signal Processing Conference, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
A distributed cellular GA based architecture for real time GPS attitude determination.
Proceedings of the IEEE Congress on Evolutionary Computation, 2009
Effect of a Central Antenna Element on the Directivity, Half-Power Beamwidth and Side-Lobe Level of Circular Antenna Arrays.
Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2009
Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2009
2008
IEEE Trans. Very Large Scale Integr. Syst., 2008
Efficient Implementation of WiMAX Physical Layer on Multi-core Architectures with Dynamically Reconfigurable Processors.
Scalable Comput. Pract. Exp., 2008
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008
OFDM symbol timing synchronization system on a Reconfigurable Instruction Cell Array.
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008
Exploiting loop-level parallelism on multi-core architectures for the wimax physical layer.
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008
MRPSIM: A TLM based simulation tool for MPSOCS targeting dynamically reconfigurable processors.
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008
Evaluation of contrast limited adaptive histogram equalization (CLAHE) enhancement on a FPGA.
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008
Multi-core Architectures with Dynamically Reconfigurable Array Processors for the WiMAX Physical Layer.
Proceedings of the IEEE Symposium on Application Specific Processors, 2008
Scalability of a Novel Shifting Balance Theory-Based Optimization Algorithm: A Comparative Study on a Cluster-Based Wireless Sensor Network.
Proceedings of the Evolvable Systems: From Biology to Hardware, 2008
Dynamically programmable Reed Solomon processor with embedded Galois Field multiplier.
Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008
SystemC-based Custom Reconfigurable Cores for Wireless Applications.
Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2008
Implementation of Hardware Encryption Engine for Wireless Communication on a Reconfigurable Instruction Cell Architecture.
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008
Efficient Implementation of Wireless Applications on Multi-core Platforms Based on Dynamically Reconfigurable Processors.
Proceedings of the Second International Conference on Complex, 2008
A novel shifting balance theory-based approach to optimization of an energy-constrained modulation scheme for wireless sensor networks.
Proceedings of the IEEE Congress on Evolutionary Computation, 2008
Proceedings of the IEEE Congress on Evolutionary Computation, 2008
Proceedings of the 2008 ECSIS Symposium on Bio-inspired, 2008
Adaptive Formation Control and Bio-inspired Optimization of a Cluster-based Satellite Wireless Sensor Network.
Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2008
Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2008
Distributed Adaptability and Mobility in Space Based Wireless Pico-Satellite Sensor Networks.
Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2008
Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2008
Addressing Future Space Challenges using Reconfigurable Instruction Cell Based Architectures.
Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2008
Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2008
2007
Low Power Implementation for Minimum Norm Sorting and Block Upper Tri-angularization of Matrices used in MIMO Wireless Systems.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007
A Power and Area Efficient Maximum Likelihood Detector Implementation for High Throughput MIMO Systems.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007
Proceedings of the 2007 IEEE International SOC Conference, 2007
Power evaluation of the arbitration policy for different on-chip bus based SoC platform.
Proceedings of the 2007 IEEE International SOC Conference, 2007
A fast pull-in scheme of plls using a triple path nonlinear phase frequency detector.
Proceedings of the 2007 IEEE International SOC Conference, 2007
Performance analysis of IEEE defined LDPC codes under various decoding algorithms and their implementation on a reconfigurable instruction cell architecture.
Proceedings of the 2007 IEEE International SOC Conference, 2007
Proceedings of the 2007 IEEE International SOC Conference, 2007
Low Computation and Memory Access for Variable Block Size Motion Estimation Using Pixel Truncation.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007
Proceedings of the International Symposium on System-on-Chip, 2007
Integrated Heterogenous Modelling for Power Estimation of Single Processor based Reconfigurable SoC Platform.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Code Compression and Decompression for Instruction Cell Based Reconfigurable Systems.
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007
System-Level Modeling and Multi-objective Evolutionary Design of Pipelined FFT Processors for Wireless OFDM Receivers.
Proceedings of the Evolvable Systems: From Biology to Hardware, 2007
Algorithmic Level Design Space Exploration Tool for Creation of Highly Optimized Synthesizable Circuits.
Proceedings of the IEEE International Conference on Acoustics, 2007
The Design of Multitasking Based Applications on Reconfigurable Instruction Cell Bsed Architectures.
Proceedings of the FPL 2007, 2007
System-level Modelling and Analysis of Embedded Reconfigurable Cores for Wireless Systems.
Proceedings of the FPL 2007, 2007
Mapping Real Time Operating System on Reconfigurable Instruction Cell Based Architectures.
Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, 2007
Code Compressor and Decompressor for Ultra Large Instruction Width Coarse-Grain Reconfigurable Systems.
Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, 2007
A new pipelined implementation for minimum norm sorting used in square root algorithm for MIMO-VBLAST systems.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
An Improved Particle Swarm Optimization Algorithm for Power-Efficient Wireless Sensor Networks.
Proceedings of the 2007 ECSIS Symposium on Bio-inspired, 2007
Proceedings of the 2007 ECSIS Symposium on Bio-inspired, 2007
A Novel Reconfigurable Low Power Distributed Arithmetic Architecture for Multimedia Applications.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
Multiobjective Optimal Design of MEMS-Based Reconfigurable and Evolvable Sensor Networks for Space Applications.
Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 2007
Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 2007
Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 2007
High Performance Embedded Reconfigurable Concatenated Convolution- Puncturing Fabric for 802.16.
Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 2007
2006
Analysis and Implementation of Multiple-Input, Multiple-Output VBLAST Receiver From Area and Power Efficiency Perspective.
IEEE Trans. Very Large Scale Integr. Syst., 2006
An Efficient Pre-Traceback Architecture for the Viterbi Decoder Targeting Wireless Communication Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2006
A Novel Architecture Using the Decorrelating Transform for Low Power Adaptive Filters.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006
Area and Power Efficient VLSI Architecture for Computing Pseudo Inverse of Channel Matrix in a MIMO Wireless System.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006
Enhanced Dual Strategy based VLSI Architecture for Computing Pseudo Inverse of Channel Matrix in a MIMO Wireless System.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006
A Low Power Pipelined Maximum Likelihood Detector for 4x4 QPSK MIMO Wireless Communication Systems.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the 2006 IEEE International Conference on Acoustics Speech and Signal Processing, 2006
Proceedings of the 2006 IEEE International Conference on Acoustics Speech and Signal Processing, 2006
Low Power Programmable FIR Filtering IP Cores Targeting System-on-a-Reprogrammable-Chip (SoRC).
Proceedings of the 2006 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2006
Proceedings of the First NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2006), 2006
A Multi-Objective Genetic Algorithm for On-Chip Real-time Adaptation of a Multi-Carrier Based Telecommunications Receiver.
Proceedings of the First NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2006), 2006
Proceedings of the First NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2006), 2006
Proceedings of the First NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2006), 2006
ESPACENET: A Framework of Evolvable and Reconfigurable Sensor Networks for Aerospace-Based Monitoring and Diagnostics.
Proceedings of the First NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2006), 2006
Proceedings of the First NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2006), 2006
2005
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005
A Novel Bus Encoding Scheme from Energy and Crosstalk Efficiency Perspective for AMBA Based Generic SoC Systems.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005
A Low Power Heterogenous Reconfigurable Architecture For Embedded Generic Finite State Machines.
Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005
A Power Efficient Reconfigurable Max-Log-MAP Turbo Decoder for Wireless Communication Systems.
Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005
High Speed Max-Log-MAP Turbo SISO Decoder Implementation Using Branch Metric Normalization.
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
A Low-Power and Domain-Specific Reconfigurable FFT Fabric for System-on-Chip Applications.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005
Multiplier-less based parallel-pipelined FFT architectures for wireless communication applications.
Proceedings of the 2005 IEEE International Conference on Acoustics, 2005
Implementation of an efficient two-step SOVA turbo decoder for wireless communication systems.
Proceedings of the Global Telecommunications Conference, 2005. GLOBECOM '05, St. Louis, Missouri, USA, 28 November, 2005
The development of high performance FFT IP cores through hybrid low power algorithmic methodology.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
2004
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004
An efficient reformulation based architecture for adaptive forward error correction decoding in wireless applications.
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004
Proceedings of the Integrated Circuit and System Design, 2004
Proceedings of the 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'04), 2004
Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004
Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004
2003
Crosstalk Immune Coding from Area and Power Perspective for high performance AMBA based SoC systems.
Proceedings of the IFIP VLSI-SoC 2003, 2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
2002
A Combined Coefficient Segmentation and Block Processing Algorithm for Low Power Implementation of FIR Digital Filters.
VLSI Design, 2002
Eur. Trans. Telecommun., 2002
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
Proceedings of the 11th European Signal Processing Conference, 2002
2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
2000
A hybrid segmentation and block processing algorithm for low power implementation of digital filters.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
An order based segmentation algorithm for low power implementation of digital filters.
Proceedings of the IEEE International Conference on Acoustics, 2000
1999
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999