Isaac Bruce

Orcid: 0000-0003-3959-1293

According to our database1, Isaac Bruce authored at least 11 papers between 2021 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Bibliography

2023
A Weighted-Bin Difference Method for Issue Site Identification in Analog and Mixed-Signal Multi-Site Testing.
J. Electron. Test., February, 2023

Ultra-Small Area, Highly Linear Sub-Radix R-2R Digital-To-Analog Converters with Novel Calibration Algorithm.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

Small Area, High Accuracy Sub-Radix Resistive Current Mode Digital-To-Analog Converter with Novel Calibration Algorithm.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

2022
A Polynomial Transform Method for Hardware Systematic Error Identification and Correction in Semiconductor Multi-Site Testing.
J. Electron. Test., December, 2022

The Least-Squares Approach to Systematic Error Identification and Calibration in Semiconductor Multisite Testing.
Proceedings of the 40th IEEE VLSI Test Symposium, 2022

Optimal Order Polynomial Transformation for Calibrating Systematic Errors in Multisite Testing.
Proceedings of the IEEE International Test Conference, 2022

Graph Theory Approach for Multi-site ATE Board Parameter Extraction.
Proceedings of the IEEE European Test Symposium, 2022

Cross-Correlation Approach to Detecting Issue Test Sites in Massive Parallel Testing.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2022

2021
Systematic Hardware Error Identification and Calibration for Massive Multisite Testing.
Proceedings of the IEEE International Test Conference, 2021

An Ordinal Optimization-Based Approach To Die Distribution Estimation For Massive Multi-site Testing Validation: A Case Study.
Proceedings of the 26th IEEE European Test Symposium, 2021

Massive Multisite Variability-Aware Die Distribution Estimation for Analog/Mixed-Signal Circuits Test Validation.
Proceedings of the 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2021


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