Shravan K. Chaganti
Orcid: 0000-0001-5930-5894
According to our database1,
Shravan K. Chaganti
authored at least 25 papers
between 2015 and 2023.
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Bibliography
2023
Site-to-Site Variation in Analog Multisite Testing: A Survey on Its Detection and Correction.
IEEE Des. Test, October, 2023
A Weighted-Bin Difference Method for Issue Site Identification in Analog and Mixed-Signal Multi-Site Testing.
J. Electron. Test., February, 2023
An Improved Single-Temperature Trim Technique for 1<sup>st</sup> Order-Compensated Bandgap References.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023
2022
A Polynomial Transform Method for Hardware Systematic Error Identification and Correction in Semiconductor Multi-Site Testing.
J. Electron. Test., December, 2022
The Least-Squares Approach to Systematic Error Identification and Calibration in Semiconductor Multisite Testing.
Proceedings of the 40th IEEE VLSI Test Symposium, 2022
Optimal Order Polynomial Transformation for Calibrating Systematic Errors in Multisite Testing.
Proceedings of the IEEE International Test Conference, 2022
Proceedings of the IEEE International Test Conference, 2022
Proceedings of the IEEE European Test Symposium, 2022
Cross-Correlation Approach to Detecting Issue Test Sites in Massive Parallel Testing.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2022
2021
Detection of Site to Site Variations From Volume Measurement Data in Multisite Semiconductor Testing.
IEEE Trans. Instrum. Meas., 2021
Systematic Hardware Error Identification and Calibration for Massive Multisite Testing.
Proceedings of the IEEE International Test Conference, 2021
An Ordinal Optimization-Based Approach To Die Distribution Estimation For Massive Multi-site Testing Validation: A Case Study.
Proceedings of the 26th IEEE European Test Symposium, 2021
Massive Multisite Variability-Aware Die Distribution Estimation for Analog/Mixed-Signal Circuits Test Validation.
Proceedings of the 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2021
2020
IEEE Trans. Instrum. Meas., 2020
Quantile - Quantile Fitting Approach to Detect Site to Site Variations in Massive Multi-site Testing.
Proceedings of the 38th IEEE VLSI Test Symposium, 2020
2018
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
Fast and accurate linearity test for DACs with various architectures using segmented models.
Proceedings of the IEEE International Test Conference, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
A low-cost jitter separation and ADC spectral testing method without requiring coherent sampling.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Low-cost and accurate DAC linearity test with ultrafast segmented model identification of linearity errors and removal of measurement errors (uSMILE-ROME).
Proceedings of the IEEE International Instrumentation and Measurement Technology Conference, 2018
2017
A low-cost method for separation and accurate estimation of ADC noise, aperture jitter, and clock jitter.
Proceedings of the 35th IEEE VLSI Test Symposium, 2017
A digital clock-less pulse stretcher with application in deep sub-nanosecond pulse detection.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
2016
Accurate linearity testing with impure sinusoidal stimulus robust against flicker noise.
Proceedings of the 34th IEEE VLSI Test Symposium, 2016
Toward complete analog fault coverage with minimal observation points using a fault propagation graph.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
2015
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015