Isao Naritake

According to our database, Isao Naritake authored at least 3 papers between 1993 and 2000.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2000

A 12-ns 8-Mbyte DRAM secondary cache for a 64-bit microprocessor.

Takashi Okuda, Isao Naritake, Tadahiko Sugibayashi, Yuji Nakajima, Tatsunori Murotani

IEEE J. Solid State Circuits, 2000

1995

A 1-Gb DRAM for file applications.

Tadahiko Sugibayashi, Isao Naritake, Satoshi Utsugi, Kentaro Shibahara, Ryuichi Oikawa, Hidemitsu Mori, Shouichi Iwao, Tatsunori Murotani, Kuniaki Koyama, Shinichi Fukuzawa, Toshiro Itani, Kunihiko Kasama, Takashi Okuda, Shuichi Ohya, Masaki Ogawa

IEEE J. Solid State Circuits, November, 1995

1993

A 30-ns 256-Mb DRAM with a multidivided array structure.

Tadahiko Sugibayashi, Toshio Takeshima, Isao Naritake, Tatsuya Matano, Hiroshi Takada, Yoshiharu Aimoto, Koichiro Furuta, Mamoru Fujita, Takanori Saeki, Hiroshi Sugawara, Tatsunori Murotani, Naoki Kasai, Kentaro Shibahara, Ken Nakajima, Hiromitsu Hada, Takehiko Hamada, Naoaki Aizaki, Takemitsu Kunio, Eiichiro Kakehashi, Katsuhiro Masumori, Takaho Tanigawa

IEEE J. Solid State Circuits, November, 1993