Ismail Emir Yuksel

Orcid: 0000-0003-3310-4423

According to our database1, Ismail Emir Yuksel authored at least 27 papers between 2020 and 2025.

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Bibliography

2025
In-DRAM True Random Number Generation Using Simultaneous Multiple-Row Activation: An Experimental Study of Real DRAM Chips.
CoRR, October, 2025

ColumnDisturb: Understanding Column-based Read Disturbance in Real DRAM Chips and Implications for Future Systems.
CoRR, October, 2025

Understanding and Mitigating Side and Covert Channel Vulnerabilities Introduced by RowHammer Defenses.
CoRR, March, 2025

Artifact of "Chronus: Understanding and Securing the Cutting-Edge Industry Solutions to DRAM Read Disturbance".
Dataset, January, 2025

Revisiting DRAM Read Disturbance: Identifying Inconsistencies Between Experimental Characterization and Device-Level Studies.
Proceedings of the 43rd IEEE VLSI Test Symposium, 2025

PuDHammer: Experimental Analysis of Read Disturbance Effects of Processing-using-DRAM in Real DRAM Chips.
Proceedings of the 52nd Annual International Symposium on Computer Architecture, 2025

Memory-Centric Computing: Solving Computing's Memory Problem.
Proceedings of the IEEE International Memory Workshop, 2025

Understanding RowHammer Under Reduced Refresh Latency: Experimental Analysis of Real DRAM Chips and Implications on Future Solutions.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2025

Variable Read Disturbance: An Experimental Analysis of Temporal Variation in DRAM Read Disturbance.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2025

Chronus: Understanding and Securing the Cutting-Edge Industry Solutions to DRAM Read Disturbance.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2025

Revisiting Main Memory-Based Covert and Side Channel Attacks in the Context of Processing-in-Memory.
Proceedings of the 55th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2025

2024
Memory-Centric Computing: Recent Advances in Processing-in-DRAM.
CoRR, 2024

Leveraging Adversarial Detection to Enable Scalable and Low Overhead RowHammer Mitigations.
CoRR, 2024

Amplifying Main Memory-Based Timing Covert and Side Channels using Processing-in-Memory Operations.
CoRR, 2024

ABACuS: All-Bank Activation Counters for Scalable and Low Overhead RowHammer Mitigation.
Proceedings of the 33rd USENIX Security Symposium, 2024

BreakHammer: Enhancing RowHammer Mitigations by Carefully Throttling Suspect Threads.
Proceedings of the 57th IEEE/ACM International Symposium on Microarchitecture, 2024

Functionally-Complete Boolean Logic in Real DRAM Chips: Experimental Characterization and Analysis.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024

Spatial Variation-Aware Read Disturbance Defenses: Experimental Analysis of Real DRAM Chips and Implications on Future Solutions.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024

CoMeT: Count-Min-Sketch-based Row Tracking to Mitigate RowHammer at Low Cost.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024

Simultaneous Many-Row Activation in Off-the-Shelf DRAM Chips: Experimental Characterization and Analysis.
Proceedings of the 54th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2024

An Experimental Characterization of Combined RowHammer and RowPress Read Disturbance in Modern DRAM Chips.
Proceedings of the 54th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2024

2023
PULSAR: Simultaneous Many-Row Activation for Reliable and High-Performance Computing in Off-the-Shelf DRAM Chips.
CoRR, 2023

2022
MoRS: An Approximate Fault Modeling Framework for Reduced-Voltage SRAMs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

TuRaN: True Random Number Generation Using Supply Voltage Underscaling in SRAMs.
CoRR, 2022

2021
MoRS: An Approximate Fault Modelling Framework for Reduced-Voltage SRAMs.
CoRR, 2021

2020
Demonstrating Reduced-Voltage FPGA-Based Neural Network Acceleration for Power-Efficiency.
Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020

An Experimental Study of Reduced-Voltage Operation in Modern FPGAs for Neural Network Acceleration.
Proceedings of the 50th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2020


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