Nisa Bostanci
Orcid: 0000-0002-2718-0297
According to our database1,
Nisa Bostanci authored at least 32 papers
between 2021 and 2026.
Collaborative distances:
Collaborative distances:
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Bibliography
2026
HE-PIM: Demystifying Homomorphic Operations on a Real-world Processing-in-Memory System.
CoRR, May, 2026
DiscoRD: An Experimental Methodology for Quickly Discovering the Reliable Read Disturbance Threshold of Real DRAM Chips.
CoRR, March, 2026
Cleaning up the Mess: Re-Evaluating the Real-System Modeling Accuracy of Ramulator 2.0.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2026
2025
Understanding and Mitigating Side and Covert Channel Vulnerabilities Introduced by RowHammer Defenses.
CoRR, March, 2025
Artifact of "Chronus: Understanding and Securing the Cutting-Edge Industry Solutions to DRAM Read Disturbance".
Dataset, January, 2025
ColumnDisturb: Understanding Column-based Read Disturbance in Real DRAM Chips and Implications for Future Systems.
Proceedings of the 58th IEEE/ACM International Symposium on Microarchitecture, 2025
Understanding and Mitigating Covert Channel and Side Channel Vulnerabilities Introduced by RowHammer Defenses.
Proceedings of the 58th IEEE/ACM International Symposium on Microarchitecture, 2025
PuDHammer: Experimental Analysis of Read Disturbance Effects of Processing-using-DRAM in Real DRAM Chips.
Proceedings of the 52nd Annual International Symposium on Computer Architecture, 2025
In-DRAM True Random Number Generation Using Simultaneous Multiple-Row Activation: An Experimental Study of Real DRAM Chips.
Proceedings of the 43rd IEEE International Conference on Computer Design, 2025
Understanding RowHammer Under Reduced Refresh Latency: Experimental Analysis of Real DRAM Chips and Implications on Future Solutions.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2025
Variable Read Disturbance: An Experimental Analysis of Temporal Variation in DRAM Read Disturbance.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2025
Chronus: Understanding and Securing the Cutting-Edge Industry Solutions to DRAM Read Disturbance.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2025
Revisiting Main Memory-Based Covert and Side Channel Attacks in the Context of Processing-in-Memory.
Proceedings of the 55th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2025
Virtuoso: Enabling Fast and Accurate Virtual Memory Research via an Imitation-based Operating System Simulation Methodology.
Proceedings of the 30th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2025
2024
Sectored DRAM: A Practical Energy-Efficient and High-Performance Fine-Grained DRAM Architecture.
ACM Trans. Archit. Code Optim., September, 2024
Amplifying Main Memory-Based Timing Covert and Side Channels using Processing-in-Memory Operations.
CoRR, 2024
MIMDRAM: An End-to-End Processing-Using-DRAM System for High-Throughput, Energy-Efficient and Programmer-Transparent Multiple-Instruction Multiple-Data Processing.
CoRR, 2024
IEEE Comput. Archit. Lett., 2024
ABACuS: All-Bank Activation Counters for Scalable and Low Overhead RowHammer Mitigation.
Proceedings of the 33rd USENIX Security Symposium, 2024
Functionally-Complete Boolean Logic in Real DRAM Chips: Experimental Characterization and Analysis.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024
MIMDRAM: An End-to-End Processing-Using-DRAM System for High-Throughput, Energy-Efficient and Programmer-Transparent Multiple-Instruction Multiple-Data Computing.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024
Simultaneous Many-Row Activation in Off-the-Shelf DRAM Chips: Experimental Characterization and Analysis.
Proceedings of the 54th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2024
2023
PULSAR: Simultaneous Many-Row Activation for Reliable and High-Performance Computing in Off-the-Shelf DRAM Chips.
CoRR, 2023
Victima: Drastically Increasing Address Translation Reach by Leveraging Underutilized Cache Resources.
Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023
Utopia: Fast and Efficient Address Translation via Hybrid Restrictive & Flexible Virtual-to-Physical Address Mappings.
Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023
2022
MetaSys: A Practical Open-source Metadata Management System to Implement and Evaluate Cross-layer Optimizations.
ACM Trans. Archit. Code Optim., 2022
CoRR, 2022
Sectored DRAM: An Energy-Efficient High-Throughput and Practical Fine-Grained DRAM Architecture.
CoRR, 2022
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022
2021
QUAC-TRNG: High-Throughput True Random Number Generation Using Quadruple Row Activation in Commodity DRAM Chips.
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021