Geraldo F. Oliveira
Orcid: 0000-0003-1557-4819
According to our database1,
Geraldo F. Oliveira
authored at least 48 papers
between 2017 and 2024.
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Bibliography
2024
PUMA: Efficient and Low-Cost Memory Allocation and Alignment Support for Processing-Using-Memory Architectures.
CoRR, 2024
MIMDRAM: An End-to-End Processing-Using-DRAM System for High-Throughput, Energy-Efficient and Programmer-Transparent Multiple-Instruction Multiple-Data Processing.
CoRR, 2024
Functionally-Complete Boolean Logic in Real DRAM Chips: Experimental Characterization and Analysis.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024
Spatial Variation-Aware Read Disturbance Defenses: Experimental Analysis of Real DRAM Chips and Implications on Future Solutions.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024
MIMDRAM: An End-to-End Processing-Using-DRAM System for High-Throughput, Energy-Efficient and Programmer-Transparent Multiple-Instruction Multiple-Data Computing.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024
2023
IEEE Trans. Emerg. Top. Comput., 2023
PULSAR: Simultaneous Many-Row Activation for Reliable and High-Performance Computing in Off-the-Shelf DRAM Chips.
CoRR, 2023
ABACuS: All-Bank Activation Counters for Scalable and Low Overhead RowHammer Mitigation.
CoRR, 2023
TransPimLib: A Library for Efficient Transcendental Functions on Processing-in-Memory Systems.
CoRR, 2023
Extending Memory Capacity in Modern Consumer Systems With Emerging Non-Volatile Memory: Experimental Analysis and Characterization Using the Intel Optane SSD.
IEEE Access, 2023
IEEE Access, 2023
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2023
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2023
2022
Dataset, July, 2022
Accelerating Neural Network Inference With Processing-in-DRAM: From the Edge to the Cloud.
IEEE Micro, 2022
RevaMp3D: Architecting the Processor Core and Cache Hierarchy for Systems with Monolithically-Integrated Logic and Memory.
CoRR, 2022
Sectored DRAM: An Energy-Efficient High-Throughput and Practical Fine-Grained DRAM Architecture.
CoRR, 2022
An Experimental Evaluation of Machine Learning Training on a Real Processing-in-Memory System.
CoRR, 2022
Enabling High-Performance and Energy-Efficient Hybrid Transactional/Analytical Databases with Hardware/Software Cooperation.
CoRR, 2022
Benchmarking a New Paradigm: Experimental Analysis and Characterization of a Real Processing-in-Memory System.
IEEE Access, 2022
Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022
Flash-Cosmos: In-Flash Bulk Bitwise Operations Using Inherent Computation Capability of NAND Flash Memory.
Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022
Methodologies, Workloads, and Tools for Processing-in-Memory: Enabling the Adoption of Data-Centric Architectures.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022
Heterogeneous Data-Centric Architectures for Modern Data-Intensive Applications: Case Studies in Machine Learning and Databases.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022
Polynesia: Enabling High-Performance and Energy-Efficient Hybrid Transactional/Analytical Databases with Hardware/Software Co-Design.
Proceedings of the 38th IEEE International Conference on Data Engineering, 2022
2021
Extending Memory Capacity in Consumer Devices with Emerging Non-Volatile Memory: An Experimental Study.
CoRR, 2021
Benchmarking a New Paradigm: An Experimental Analysis of a Real Processing-in-Memory Architecture.
CoRR, 2021
pLUTo: In-DRAM Lookup Tables to Enable Massively Parallel General-Purpose Computation.
CoRR, 2021
Polynesia: Enabling Effective Hybrid Transactional/Analytical Databases with Specialized Hardware/Software Co-Design.
CoRR, 2021
Mitigating Edge Machine Learning Inference Bottlenecks: An Empirical Study on Accelerating Google Edge Models.
CoRR, 2021
DAMOV: A New Methodology and Benchmark Suite for Evaluating Data Movement Bottlenecks.
IEEE Access, 2021
HARP: Practically and Effectively Identifying Uncorrectable Errors in Memory Chips That Use On-Die Error-Correcting Codes.
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021
Benchmarking Memory-Centric Computing Systems: Analysis of Real Processing-In-Memory Hardware.
Proceedings of the 12th International Green and Sustainable Computing Workshops, 2021
Proceedings of the ASPLOS '21: 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2021
Google Neural Network Models for Edge Devices: Analyzing and Mitigating Machine Learning Inference Bottlenecks.
Proceedings of the 30th International Conference on Parallel Architectures and Compilation Techniques, 2021
2020
The Virtual Block Interface: A Flexible Alternative to the Conventional Virtual Memory Framework.
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020
2019
NAPEL: Near-Memory Computing Application Performance Prediction via Ensemble Learning.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
2018
Proceedings of the VIII Brazilian Symposium on Computing Systems Engineering, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Proceedings of the 55th Annual Design Automation Conference, 2018
2017
A generic processing in memory cycle accurate simulator under hybrid memory cube architecture.
Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Proceedings of the Applied Reconfigurable Computing - 13th International Symposium, 2017