Yahya Can Tugrul

Orcid: 0009-0002-9291-3626

According to our database1, Yahya Can Tugrul authored at least 15 papers between 2021 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
CoMeT: Count-Min-Sketch-based Row Tracking to Mitigate RowHammer at Low Cost.
CoRR, 2024

Functionally-Complete Boolean Logic in Real DRAM Chips: Experimental Characterization and Analysis.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024

Spatial Variation-Aware Read Disturbance Defenses: Experimental Analysis of Real DRAM Chips and Implications on Future Solutions.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024

CoMeT: Count-Min-Sketch-based Row Tracking to Mitigate RowHammer at Low Cost.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024

2023
DRAM Bender: An Extensible and Versatile FPGA-Based Infrastructure to Easily Test State-of-the-Art DRAM Chips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023

PULSAR: Simultaneous Many-Row Activation for Reliable and High-Performance Computing in Off-the-Shelf DRAM Chips.
CoRR, 2023

Understanding Read Disturbance in High Bandwidth Memory: An Experimental Analysis of Real HBM2 DRAM Chips.
CoRR, 2023

ABACuS: All-Bank Activation Counters for Scalable and Low Overhead RowHammer Mitigation.
CoRR, 2023

Ramulator 2.0: A Modern, Modular, and Extensible DRAM Simulator.
CoRR, 2023

RowPress: Amplifying Read Disturbance in Modern DRAM Chips.
Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023

DEV-PIM: Dynamic Execution Validation with Processing-in-Memory.
Proceedings of the IEEE European Test Symposium, 2023

An Experimental Analysis of RowHammer in HBM2 DRAM Chips.
Proceedings of the 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2023

2022
TuRaN: True Random Number Generation Using Supply Voltage Underscaling in SRAMs.
CoRR, 2022

Sectored DRAM: An Energy-Efficient High-Throughput and Practical Fine-Grained DRAM Architecture.
CoRR, 2022

2021
Uncovering In-DRAM RowHammer Protection Mechanisms: A New Methodology, Custom RowHammer Patterns, and Implications.
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021


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