Konstantinos Kanellopoulos

Orcid: 0000-0002-2375-7490

According to our database1, Konstantinos Kanellopoulos authored at least 23 papers between 2019 and 2024.

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Bibliography

2024
Virtuoso: An Open-Source, Comprehensive and Modular Simulation Framework for Virtual Memory Research.
CoRR, 2024

CoMeT: Count-Min-Sketch-based Row Tracking to Mitigate RowHammer at Low Cost.
CoRR, 2024

Address Scaling: Architectural Support for Fine-Grained Thread-Safe Metadata Management.
IEEE Comput. Archit. Lett., 2024

CoMeT: Count-Min-Sketch-based Row Tracking to Mitigate RowHammer at Low Cost.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024

2023
PiDRAM: A Holistic End-to-end FPGA-based Framework for Processing-in-DRAM.
ACM Trans. Archit. Code Optim., March, 2023

ALP: Alleviating CPU-Memory Data Movement Overheads in Memory-Centric Systems.
IEEE Trans. Emerg. Top. Comput., 2023

Victima: Drastically Increasing Address Translation Reach by Leveraging Underutilized Cache Resources.
Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023

Utopia: Fast and Efficient Address Translation via Hybrid Restrictive & Flexible Virtual-to-Physical Address Mappings.
Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023

Evaluating Homomorphic Operations on a Real-World Processing-In-Memory System.
Proceedings of the IEEE International Symposium on Workload Characterization, 2023

2022
MetaSys: A Practical Open-source Metadata Management System to Implement and Evaluate Cross-layer Optimizations.
ACM Trans. Archit. Code Optim., 2022

Utopia: Efficient Address Translation using Hybrid Virtual-to-Physical Address Mapping.
CoRR, 2022

RevaMp3D: Architecting the Processor Core and Cache Hierarchy for Systems with Monolithically-Integrated Logic and Memory.
CoRR, 2022

EcoFlow: Efficient Convolutional Dataflows for Low-Power Neural Network Accelerators.
CoRR, 2022

Hermes: Accelerating Long-Latency Load Requests via Perceptron-Based Off-Chip Load Prediction.
Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022

PiDRAM: An FPGA-based Framework for End-to-end Evaluation of Processing-in-DRAM Techniques.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

SeGraM: a universal hardware accelerator for genomic sequence-to-graph and sequence-to-sequence mapping.
Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022

2021
SISA: Set-Centric Instruction Set Architecture for Graph Mining on Processing-in-Memory Systems.
CoRR, 2021

SISA: Set-Centric Instruction Set Architecture for Graph Mining on Processing-in-Memory Systems.
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

Pythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement Learning.
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

BlockHammer: Preventing RowHammer at Low Cost by Blacklisting Rapidly-Accessed DRAM Rows.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021

2020
The Virtual Block Interface: A Flexible Alternative to the Conventional Virtual Memory Framework.
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

2019
EDEN: Enabling Energy-Efficient, High-Performance Deep Neural Network Inference Using Approximate DRAM.
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

SMASH: Co-designing Software Compression and Hardware-Accelerated Indexing for Efficient Sparse Matrix Operations.
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019


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